| /external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/bidi/ |
| D | TestBidiTransform.java | 16 import com.ibm.icu.text.BidiTransform.Order;
79 String outText = bidiTransform.transform(inText, inLevel, Order.LOGICAL, in autoDirectionTest()
80 outLevel, Order.VISUAL, Mirroring.OFF, 0); in autoDirectionTest()
108 { Bidi.LTR, Order.LOGICAL, Bidi.LTR, Order.LOGICAL, in allTransformOptionsTest()
113 { Bidi.LTR, Order.LOGICAL, Bidi.LTR, Order.VISUAL, in allTransformOptionsTest()
118 { Bidi.LTR, Order.LOGICAL, Bidi.RTL, Order.LOGICAL, in allTransformOptionsTest()
123 { Bidi.LTR, Order.LOGICAL, Bidi.RTL, Order.VISUAL, in allTransformOptionsTest()
129 { Bidi.RTL, Order.LOGICAL, Bidi.RTL, Order.LOGICAL, inText, in allTransformOptionsTest()
133 { Bidi.RTL, Order.LOGICAL, Bidi.RTL, Order.VISUAL, in allTransformOptionsTest()
138 { Bidi.RTL, Order.LOGICAL, Bidi.LTR, Order.LOGICAL, in allTransformOptionsTest()
[all …]
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| /external/icu/android_icu4j/src/main/tests/android/icu/dev/test/bidi/ |
| D | TestBidiTransform.java | 17 import android.icu.text.BidiTransform.Order;
82 String outText = bidiTransform.transform(inText, inLevel, Order.LOGICAL, in autoDirectionTest()
83 outLevel, Order.VISUAL, Mirroring.OFF, 0); in autoDirectionTest()
111 { Bidi.LTR, Order.LOGICAL, Bidi.LTR, Order.LOGICAL, in allTransformOptionsTest()
116 { Bidi.LTR, Order.LOGICAL, Bidi.LTR, Order.VISUAL, in allTransformOptionsTest()
121 { Bidi.LTR, Order.LOGICAL, Bidi.RTL, Order.LOGICAL, in allTransformOptionsTest()
126 { Bidi.LTR, Order.LOGICAL, Bidi.RTL, Order.VISUAL, in allTransformOptionsTest()
132 { Bidi.RTL, Order.LOGICAL, Bidi.RTL, Order.LOGICAL, inText, in allTransformOptionsTest()
136 { Bidi.RTL, Order.LOGICAL, Bidi.RTL, Order.VISUAL, in allTransformOptionsTest()
141 { Bidi.RTL, Order.LOGICAL, Bidi.LTR, Order.LOGICAL, in allTransformOptionsTest()
[all …]
|
| /external/libcxx/benchmarks/ |
| D | algorithms.bench.cpp | 26 enum class Order { enum
34 struct AllOrders : EnumValuesAsTuple<AllOrders, Order, 6> {
40 void fillValues(std::vector<uint32_t>& V, size_t N, Order O) { in fillValues()
41 if (O == Order::SingleElement) { in fillValues()
49 void fillValues(std::vector<std::string>& V, size_t N, Order O) { in fillValues()
51 if (O == Order::SingleElement) { in fillValues()
60 void sortValues(T& V, Order O) { in sortValues()
63 case Order::Random: { in sortValues()
69 case Order::Ascending: in sortValues()
72 case Order::Descending: in sortValues()
[all …]
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| /external/icu/android_icu4j/src/main/java/android/icu/text/ |
| D | BidiTransform.java | 57 public enum Order { enum in BidiTransform
212 byte inParaLevel, Order inOrder, in transform()
213 byte outParaLevel, Order outOrder, in transform()
270 private ReorderingScheme findMatchingScheme(byte inLevel, Order inOrder, in findMatchingScheme()
271 byte outLevel, Order outOrder) { in findMatchingScheme()
370 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
383 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
396 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
410 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
424 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
[all …]
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| /external/icu/icu4j/main/classes/core/src/com/ibm/icu/text/ |
| D | BidiTransform.java | 56 public enum Order { enum in BidiTransform
222 byte inParaLevel, Order inOrder, in transform()
223 byte outParaLevel, Order outOrder, in transform()
280 private ReorderingScheme findMatchingScheme(byte inLevel, Order inOrder, in findMatchingScheme()
281 byte outLevel, Order outOrder) { in findMatchingScheme()
380 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
393 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
406 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
420 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
434 boolean matches(byte inLevel, Order inOrder, byte outLevel, Order outOrder) { in matches()
[all …]
|
| /external/libopus/silk/float/ |
| D | corrMatrix_FLP.c | 43 …const opus_int Order, /* I Max lag for correlatio… in silk_corrVector_FLP() argument
50 … ptr1 = &x[ Order - 1 ]; /* Points to first sample of column 0 of X: X[:,0] */ in silk_corrVector_FLP()
51 for( lag = 0; lag < Order; lag++ ) { in silk_corrVector_FLP()
62 …const opus_int Order, /* I Max lag for correlatio… in silk_corrMatrix_FLP() argument
70 ptr1 = &x[ Order - 1 ]; /* First sample of column 0 of X */ in silk_corrMatrix_FLP()
72 matrix_ptr( XX, 0, 0, Order ) = ( silk_float )energy; in silk_corrMatrix_FLP()
73 for( j = 1; j < Order; j++ ) { in silk_corrMatrix_FLP()
76 matrix_ptr( XX, j, j, Order ) = ( silk_float )energy; in silk_corrMatrix_FLP()
79 ptr2 = &x[ Order - 2 ]; /* First sample of column 1 of X */ in silk_corrMatrix_FLP()
80 for( lag = 1; lag < Order; lag++ ) { in silk_corrMatrix_FLP()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SDNodeDbgValue.h | 51 unsigned Order; variable
60 : Var(Var), Expr(Expr), DL(std::move(dl)), Order(O), IsIndirect(indir) { in SDDbgValue()
69 : Var(Var), Expr(Expr), DL(std::move(dl)), Order(O), IsIndirect(false) { in SDDbgValue()
76 bool IsIndirect, DebugLoc DL, unsigned Order, in SDDbgValue() argument
78 : Var(Var), Expr(Expr), DL(DL), Order(Order), IsIndirect(IsIndirect) { in SDDbgValue()
120 unsigned getOrder() const { return Order; } in getOrder()
134 unsigned Order; variable
138 : Label(Label), DL(std::move(dl)), Order(O) {} in SDDbgLabel()
148 unsigned getOrder() const { return Order; } in getOrder()
|
| /external/deqp/framework/referencerenderer/ |
| D | rrVertexAttrib.cpp | 59 template<typename SrcScalarType, typename DstScalarType, typename Order>
65 dst[Order::T0] = DstScalarType(aligned[0]); in readOrder()
66 if (size >= 2) dst[Order::T1] = DstScalarType(aligned[1]); in readOrder()
67 if (size >= 3) dst[Order::T2] = DstScalarType(aligned[2]); in readOrder()
68 if (size >= 4) dst[Order::T3] = DstScalarType(aligned[3]); in readOrder()
71 template<typename SrcScalarType, typename Order>
79 dst[Order::T0] = float(aligned[0]) / float(range); in readUnormOrder()
80 if (size >= 2) dst[Order::T1] = float(aligned[1]) / float(range); in readUnormOrder()
81 if (size >= 3) dst[Order::T2] = float(aligned[2]) / float(range); in readUnormOrder()
82 if (size >= 4) dst[Order::T3] = float(aligned[3]) / float(range); in readUnormOrder()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Support/ |
| D | DynamicLibrary.cpp | 77 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup() argument
78 if (Order & SO_LoadOrder) { in LibLookup()
92 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup() argument
93 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && in Lookup()
96 if (!Process || (Order & SO_LoadedFirst)) { in Lookup()
97 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
106 if (Order & SO_LoadedLast) { in Lookup()
107 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
|
| /external/cblas/include/ |
| D | cblas.h | 416 void cblas_sgemm(const enum CBLAS_ORDER Order, const enum CBLAS_TRANSPOSE TransA,
421 void cblas_ssymm(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side,
426 void cblas_ssyrk(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo,
430 void cblas_ssyr2k(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo,
435 void cblas_strmm(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side,
440 void cblas_strsm(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side,
446 void cblas_dgemm(const enum CBLAS_ORDER Order, const enum CBLAS_TRANSPOSE TransA,
451 void cblas_dsymm(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side,
456 void cblas_dsyrk(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo,
460 void cblas_dsyr2k(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo,
[all …]
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 51 Order ///< Any other ordering dependency. enumerator
80 } Order; member
110 case Order: in Dep()
112 Contents.Order.isNormalMemory = isNormalMemory; in Dep()
113 Contents.Order.isMustAlias = isMustAlias; in Dep()
114 Contents.Order.isArtificial = isArtificial; in Dep()
126 case Order:
127 return Contents.Order.isNormalMemory ==
128 Other.Contents.Order.isNormalMemory &&
129 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AllocationOrder.cpp | 44 ArrayRef<unsigned> Order = in AllocationOrder() local
47 if (Order.empty()) in AllocationOrder()
52 unsigned *P = new unsigned[Order.size()]; in AllocationOrder()
54 for (unsigned i = 0; i != Order.size(); ++i) in AllocationOrder()
55 if (!RCI.isReserved(Order[i])) in AllocationOrder()
56 *P++ = Order[i]; in AllocationOrder()
|
| D | ScheduleDAGInstrs.cpp | 374 ExitSU.addPred(SDep(SU, SDep::Order, Latency, in BuildSchedGraph()
429 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
434 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency)); in BuildSchedGraph()
440 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
447 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
450 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency)); in BuildSchedGraph()
453 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
458 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency)); in BuildSchedGraph()
475 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0, in BuildSchedGraph()
491 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency, in BuildSchedGraph()
[all …]
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| D | RegisterClassInfo.cpp | 76 if (!RCI.Order) in compute()
77 RCI.Order.reset(new unsigned[NumRegs]); in compute()
94 RCI.Order[N++] = PhysReg; in compute()
100 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]); in compute()
110 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); in compute()
|
| D | RegAllocGreedy.cpp | 445 AllocationOrder &Order, in tryAssign() argument
447 Order.rewind(); in tryAssign()
449 while ((PhysReg = Order.next())) in tryAssign()
452 if (!PhysReg || Order.isHint(PhysReg)) in tryAssign()
460 if (Order.isHint(Hint)) { in tryAssign()
478 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); in tryAssign()
614 AllocationOrder &Order, in tryEvict() argument
630 Order.rewind(); in tryEvict()
631 while (unsigned PhysReg = Order.next()) { in tryEvict()
651 if (Order.isHint(PhysReg)) in tryEvict()
[all …]
|
| /external/llvm/lib/CodeGen/ |
| D | AllocationOrder.cpp | 37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
38 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in AllocationOrder()
51 assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() && in AllocationOrder()
|
| D | AllocationOrder.h | 31 ArrayRef<MCPhysReg> Order; variable
45 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
54 Limit = Order.size();
56 unsigned Reg = Order[Pos++];
71 return Order[Pos++]; in nextWithDups()
|
| D | RegAllocGreedy.cpp | 374 AllocationOrder &Order,
383 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
619 AllocationOrder &Order, in tryAssign() argument
621 Order.rewind(); in tryAssign()
623 while ((PhysReg = Order.next())) in tryAssign()
626 if (!PhysReg || Order.isHint()) in tryAssign()
634 if (Order.isHint(Hint)) { in tryAssign()
653 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); in tryAssign()
663 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in canReassign() local
665 while ((PhysReg = Order.next())) { in canReassign()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
50 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
61 Limit = Order.size();
63 unsigned Reg = Order[Pos++];
80 return Order[Pos++]; in nextWithDups()
|
| D | RegAllocGreedy.cpp | 456 const AllocationOrder &Order);
459 const AllocationOrder &Order);
461 const AllocationOrder &Order,
472 unsigned getCheapestEvicteeWeight(const AllocationOrder &Order,
490 AllocationOrder &Order,
500 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
760 AllocationOrder &Order, in tryAssign() argument
762 Order.rewind(); in tryAssign()
764 while ((PhysReg = Order.next())) in tryAssign()
767 if (!PhysReg || Order.isHint()) in tryAssign()
[all …]
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 527 void setIROrder(unsigned Order) { IROrder = Order; }
817 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
820 NumOperands(0), NumValues(VTs.NumVTs), IROrder(Order),
849 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
850 assert(Order >= 0 && "bad IROrder");
959 BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
961 : SDNode(Opc, Order, dl, VTs), Flags(NodeFlags) {}
999 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1021 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1153 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
[all …]
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SDNodeDbgValue.h | 50 unsigned Order; variable
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O), in SDDbgValue()
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { in SDDbgValue()
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { in SDDbgValue()
103 unsigned getOrder() { return Order; } in getOrder()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SDNodeDbgValue.h | 50 unsigned Order; variable
59 : Var(Var), Expr(Expr), Offset(off), DL(std::move(dl)), Order(O), in SDDbgValue()
69 : Var(Var), Expr(Expr), Offset(off), DL(std::move(dl)), Order(O), in SDDbgValue()
78 : Var(Var), Expr(Expr), Offset(off), DL(std::move(dl)), Order(O), in SDDbgValue()
116 unsigned getOrder() const { return Order; } in getOrder()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceIntrinsics.cpp | 261 bool isMemoryOrderValidPNaCl(uint64_t Order) { in isMemoryOrderValidPNaCl() argument
262 switch (Order) { in isMemoryOrderValidPNaCl()
275 bool Intrinsics::isMemoryOrderValid(IntrinsicID ID, uint64_t Order, in isMemoryOrderValid() argument
278 if (!isMemoryOrderValidPNaCl(Order)) in isMemoryOrderValid()
299 if (OrderOther > Order) in isMemoryOrderValid()
301 if (Order == MemoryOrderRelease && OrderOther != MemoryOrderRelaxed) in isMemoryOrderValid()
308 switch (Order) { in isMemoryOrderValid()
316 switch (Order) { in isMemoryOrderValid()
|
| /external/aac/libAACdec/src/ |
| D | aacdec_tns.cpp | 192 filter->Order = order = (UCHAR)FDKreadBits(bs, isLongFlag ? 4 : 3); in CTns_Read()
194 filter->Order = order = (UCHAR)FDKreadBits(bs, isLongFlag ? 5 : 3); in CTns_Read()
196 if (filter->Order > TNS_MAXIMUM_ORDER) { in CTns_Read()
297 if (filter->Order > 0) { in CTns_Apply()
304 for (i = 0; i < filter->Order; i++) in CTns_Apply()
308 for (i = 0; i < filter->Order; i++) in CTns_Apply()
351 filter->Direction, coeff, filter->Order, in CTns_Apply()
|