| /external/libese/libese-teq1/ |
| D | teq1.c | 120 teq1_trace_transmit(frame->header.PCB, frame->header.LEN); in teq1_transmit()
165 teq1_trace_receive(frame->header.PCB, frame->header.LEN); in teq1_receive()
185 switch (bs_get(PCB.type, frame->header.PCB)) { in teq1_fill_info_block()
209 bs_assign(&frame->header.PCB, PCB.I.more_data, 0); in teq1_fill_info_block()
211 frame->header.PCB |= bs_mask(PCB.I.more_data, 1); in teq1_fill_info_block()
224 switch (bs_get(PCB.type, frame->header.PCB)) { in teq1_get_app_data()
255 if (rx_frame->header.PCB == 255) { in teq1_frame_error_check()
267 switch (bs_get(PCB.type, tx_frame->header.PCB)) { in teq1_frame_error_check()
270 chained = bs_get(PCB.I.more_data, tx_frame->header.PCB); in teq1_frame_error_check()
272 bs_get(PCB.I.send_seq, tx_frame->header.PCB); in teq1_frame_error_check()
[all …]
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| /external/libese/libese-teq1/tests/ |
| D | teq1_unittests.cpp | 66 tx_frame_.header.PCB = TEQ1_I(0, 0); in TEST_F()
70 rx_frame_.header.PCB = *pcb; in TEST_F()
75 …teq1_frame_error_check(&state_, &tx_frame_, &rx_frame_)) << teq1_pcb_to_name(rx_frame_.header.PCB); in TEST_F()
133 tx_frame_.header.PCB = TEQ1_I(0, 0); in SetUp()
138 rx_frame_.header.PCB = TEQ1_I(0, 0); in SetUp()
148 teq1_trace_transmit(tx_frame_.header.PCB, tx_frame_.header.LEN); in RunRules()
149 teq1_trace_receive(rx_frame_.header.PCB, rx_frame_.header.LEN); in RunRules()
155 EXPECT_EQ(0, tx_next_.header.PCB) in RunRules()
156 << "Actual next TX: " << teq1_pcb_to_name(tx_next_.header.PCB); in RunRules()
182 tx_frame_.header.PCB = TEQ1_I(1, 0); in TEST_F()
[all …]
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| /external/libese/libese-teq1/include/ese/ |
| D | teq1.h | 73 const static struct PcbSpec PCB = { variable
96 uint8_t PCB; member
198 #define teq1_trace_transmit(PCB, LEN) ALOGI("%-20s --> %20s [%3hhu]", teq1_pcb_to_name(PCB), "", LE… argument
199 #define teq1_trace_receive(PCB, LEN) ALOGI("%-20s <-- %20s [%3hhu]", "", teq1_pcb_to_name(PCB), LEN) argument
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.td | 29 def PCB : MSP430Reg<0, "r0">;
49 def PC : MSP430RegWithSubregs<0, "r0", [PCB]>;
73 PCB, SPB, SRB, CGB)>;
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| D | MSP430RegisterInfo.cpp | 79 Reserved.set(MSP430::PCB); in getReservedRegs()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.td | 29 def PCB : MSP430Reg<0, "r0">;
49 def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
73 PCB, SPB, SRB, CGB)>;
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| D | MSP430RegisterInfo.cpp | 82 Reserved.set(MSP430::PCB); in getReservedRegs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.td | 29 def PCB : MSP430Reg<0, "r0">;
49 def PC : MSP430RegWithSubregs<0, "r0", [PCB]>;
73 PCB, SPB, SRB, CGB)>;
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| D | MSP430RegisterInfo.cpp | 79 Reserved.set(MSP430::PCB); in getReservedRegs()
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| /external/u-boot/drivers/video/bridge/ |
| D | Kconfig | 18 on the PCB. Setup parameters are provided in the device tree.
27 or where LVDS requires too many signals to route on the PCB.
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| /external/u-boot/arch/arm/mach-sti/ |
| D | Kconfig | 17 with PCB soldered antenna
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| /external/u-boot/arch/arm/dts/ |
| D | sun7i-a20-pcduino3-nano.dts | 66 /* Marked "LED3" on the PCB. */
72 /* Marked "LED4" on the PCB. */
|
| D | armada-xp-synology-ds414.dts | 151 /* Connected to a header on device's PCB. This
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| /external/walt/arduino/walt/ |
| D | walt.ino | 60 #define DEBUG_LED1 11 // On r0.7 PCB: D4 - Red
61 #define DEBUG_LED2 12 // On r0.7 PCB: D3 - Green
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| /external/u-boot/board/buffalo/lsxl/ |
| D | README | 6 the LS-XHL PCB has two SDRAM chips. Both have a Kirkwood CPU (Marvell
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| /external/u-boot/board/freescale/p1010rdb/ |
| D | README.P1010RDB-PB | 37 PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
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| D | README.P1010RDB-PA | 53 PCB
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| /external/u-boot/board/sbc8548/ |
| D | README | 83 the back of the PCB behind the DDR SDRAM SODIMM connector.
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| /external/walt/docs/usage/ |
| D | WALT_usage.md | 15 * Assembled WALT PCB and base, with DIP socket for Teensy LC
|
| /external/tensorflow/tensorflow/examples/udacity/ |
| D | 5_word2vec.ipynb | 869 …PCB\nIn06dOjE7NnTSi0CrpDPzyh0Ro6qqrREu09JZmYm3303HG/vgXh4DODsWYXXJiBgOY8fx+Pl5caq\nVQqjb/PmDUyaNI6…
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| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | 2013-1_UNLOCODE_CodeListPart2.csv | 8117 ,"ID","PCB","Pondok Cabe","Pondok Cabe",,"---4----","AI","0001",,,
13771 ,"IT","PCB","Pessano con Bornago","Pessano con Bornago",,"--3-----","RL","0001",,,
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| D | 2013-1_UNLOCODE_CodeListPart1.csv | 7583 ,"BR","PCB","Porto de cebedelo","Porto de cebedelo","PB","1-3-----","RQ","0901",,,
10069 ,"CA","PCB","Picture Butte","Picture Butte","AB","-23-----","RL","0701",,"4952N 11247W",
40051 ,"FR","PCB","Portel-des-Corbi�res","Portel-des-Corbieres","11","1-3-----","RL","0601",,"4303N 00255…
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| D | 2013-1_UNLOCODE_CodeListPart3.csv | 22072 ,"US","PCB","Phil Campbell","Phil Campbell","AL","-23--6--","RL","0501",,"3421N 08742W",
|