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Searched refs:PKT3 (Results 1 – 25 of 34) sorted by relevance

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/external/mesa3d/src/amd/vulkan/
Dradv_cs.h47 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
62 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
79 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
89 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
104 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
120 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); in radeon_set_uconfig_reg_idx()
Dsi_cmd_buffer.c342 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_emit_config()
347 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0)); in si_emit_config()
843 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated)); in si_cs_emit_write_event_eop()
859 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated)); in si_cs_emit_write_event_eop()
867 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated)); in si_cs_emit_write_event_eop()
882 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated)); in si_emit_wait_fence()
900 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) | in si_emit_acquire_mem()
910 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated)); in si_emit_acquire_mem()
964 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
969 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
[all …]
Dradv_cmd_buffer.c403 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); in radv_emit_write_data_packet()
427 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in radv_cmd_buffer_trace_emit()
650 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_update_multisample_state()
1029 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_fragment_shader()
1370 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0)); in radv_set_depth_clear_regs()
1409 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_load_depth_clear_regs()
1418 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in radv_load_depth_clear_regs()
1438 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); in radv_set_dcc_need_cmask_elim_pred()
1459 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); in radv_set_color_clear_regs()
1486 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating)); in radv_load_color_clear_regs()
[all …]
Dradv_query.c971 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in radv_CmdCopyQueryPoolResults()
1025 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_CmdCopyQueryPoolResults()
1034 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_CmdCopyQueryPoolResults()
1111 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in radv_CmdBeginQuery()
1119 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in radv_CmdBeginQuery()
1154 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in radv_CmdEndQuery()
1165 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in radv_CmdEndQuery()
1202 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_CmdWriteTimestamp()
1211 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); in radv_CmdWriteTimestamp()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
135 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
149 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
165 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
174 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
188 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
204 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); in radeon_set_uconfig_reg_idx()
Dr600_hw_context.c122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
136 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
142 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
156 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
230 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0)); in r600_flush_emit()
238 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
242 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
431 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in r600_emit_pfp_sync_me()
458 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0)); in r600_emit_pfp_sync_me()
464 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_pfp_sync_me()
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Dr600_streamout.c169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_vgt_streamout()
172 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in r600_flush_vgt_streamout()
212 radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0)); in r600_emit_streamout_begin()
225 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_begin()
237 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_begin()
248 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_streamout_begin()
268 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_end()
Devergreen_state.c1746 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ in evergreen_emit_image_state()
1749 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ in evergreen_emit_image_state()
1752 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */ in evergreen_emit_image_state()
1755 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */ in evergreen_emit_image_state()
1763 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/ in evergreen_emit_image_state()
1766 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); in evergreen_emit_image_state()
1770 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
1773 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); in evergreen_emit_image_state()
1777 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
1781 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
[all …]
Devergreen_hw_context.c131 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in evergreen_cp_dma_clear_buffer()
138 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in evergreen_cp_dma_clear_buffer()
Dr600_state.c1385 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1398 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1411 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1435 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_framebuffer_state()
1458 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1472 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_framebuffer_state()
1556 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_db_state()
1675 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); in r600_emit_vertex_buffers()
1687 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_vertex_buffers()
1719 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_constant_buffers()
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Dr600_pipe.h862 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT… macro
885 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); in r600_store_config_reg_seq()
897 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; in r600_store_context_reg_seq()
909 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; in r600_store_ctl_const_seq()
917 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); in r600_store_loop_const_seq()
929 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; in eg_store_loop_const_seq()
977 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0)); in radeon_set_ctl_const_seq()
Dr600_state_common.c2141 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); in r600_draw_vbo()
2151 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0)); in r600_draw_vbo()
2156 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_draw_vbo()
2164 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); in r600_draw_vbo()
2172 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit)); in r600_draw_vbo()
2180 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit)); in r600_draw_vbo()
2185 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_draw_vbo()
2194 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0)); in r600_draw_vbo()
2198 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_draw_vbo()
2204 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0)); in r600_draw_vbo()
[all …]
Dr600d_common.h40 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT… macro
Devergreen_compute.c668 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ in compute_setup_cbs()
671 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ in compute_setup_cbs()
732 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in compute_emit_cs()
804 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in compute_emit_cs()
1007 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); in evergreen_init_atom_start_compute_cs()
Dr600_query.c717 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_sample_streamout()
733 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_hw_do_emit_start()
757 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_hw_do_emit_start()
814 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_hw_do_emit_stop()
846 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_hw_do_emit_stop()
900 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0)); in emit_set_predicate()
1884 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_fix_enabled_rb_mask()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h118 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
132 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
148 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
157 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
171 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
187 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); in radeon_set_uconfig_reg_idx()
Dr600_pipe_common.c78 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_gfx_write_event_eop()
87 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0)); in si_gfx_write_event_eop()
105 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); in si_gfx_write_event_eop()
116 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); in si_gfx_write_event_eop()
149 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_gfx_wait_fence()
Dr600_query.c741 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_sample_streamout()
758 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_hw_do_emit_start()
777 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in r600_query_hw_do_emit_start()
787 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_hw_do_emit_start()
845 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_hw_do_emit_stop()
877 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in r600_query_hw_do_emit_stop()
932 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0)); in emit_set_predicate()
937 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0)); in emit_set_predicate()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.c663 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in si_emit_draw_packets()
706 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); in si_emit_draw_packets()
735 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); in si_emit_draw_packets()
750 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0)); in si_emit_draw_packets()
754 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0)); in si_emit_draw_packets()
759 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT in si_emit_draw_packets()
780 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI : in si_emit_draw_packets()
798 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); in si_emit_draw_packets()
832 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit)); in si_emit_draw_packets()
839 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit)); in si_emit_draw_packets()
[all …]
Dsi_state_streamout.c246 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_flush_vgt_streamout()
249 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_flush_vgt_streamout()
287 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_begin()
301 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_begin()
328 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_end()
Dsi_perfcounter.c590 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in si_pc_emit_start()
600 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_start()
618 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_stop()
620 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_stop()
647 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in si_pc_emit_read()
660 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in si_pc_emit_read()
Dsi_pm4.c45 PKT3(state->last_opcode, count, predicate); in si_pm4_cmd_end()
142 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0)); in si_pm4_emit()
Dsi_cp_dma.c102 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); in si_emit_cp_dma()
112 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in si_emit_cp_dma()
126 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in si_emit_cp_dma()
Dsi_compute.c694 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in si_setup_tgsi_grid()
764 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) | in si_emit_dispatch_packets()
770 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) | in si_emit_dispatch_packets()
775 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) | in si_emit_dispatch_packets()
Dsi_fence.c167 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); in si_fine_fence_set()

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