Searched refs:Pin (Results 1 – 25 of 33) sorted by relevance
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| /external/epid-sdk/epid/member/tiny/math/src/ |
| D | pairing.c | 69 static void frob_op(Fq12Elem* Pout, Fq12Elem const* Pin, int e, in frob_op() argument
72 Fq2Conj(&Pout->z0.y0, &Pin->z0.y0); in frob_op()
73 Fq2Conj(&Pout->z1.y0, &Pin->z1.y0); in frob_op()
74 Fq2Conj(&Pout->z0.y1, &Pin->z0.y1); in frob_op()
75 Fq2Conj(&Pout->z1.y1, &Pin->z1.y1); in frob_op()
76 Fq2Conj(&Pout->z0.y2, &Pin->z0.y2); in frob_op()
77 Fq2Conj(&Pout->z1.y2, &Pin->z1.y2); in frob_op()
79 Fq2Cp(&Pout->z0.y0, &Pin->z0.y0); in frob_op()
80 Fq2Cp(&Pout->z1.y0, &Pin->z1.y0); in frob_op()
81 Fq2Cp(&Pout->z0.y1, &Pin->z0.y1); in frob_op()
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| /external/u-boot/doc/device-tree-bindings/gpio/ |
| D | intel,x86-pinctrl.txt | 3 Pin-muxing on x86 can be described with a node for the PINCTRL master
9 Pin nodes must be children of the pinctrl master node and can
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| D | gpio-samsung.txt | 18 - Pin number: is a value between 0 to 7.
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| D | intel,x86-broadwell-pinctrl.txt | 3 Pin-muxing on broadwell devices can be described with a node for the PINCTRL
11 Pin state nodes must be sub-nodes of the pinctrl master node. The must have
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| /external/u-boot/doc/device-tree-bindings/pinctrl/ |
| D | st,stm32-pinctrl.txt | 1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
8 Pin controller node:
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| D | pinctrl-bindings.txt | 99 == Pin controller devices ==
101 Pin controller devices should contain the pin configuration nodes that client
162 and generic. Pin control bindings should use the properties defined below
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| /external/u-boot/board/freescale/p1022ds/ |
| D | README | 7 Pin Multiplex(hwconfig setting)
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| /external/apache-harmony/ |
| D | Android.bp | 36 // Pin java_version until jarjar is certified to support later versions. http://b/72703434
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| /external/u-boot/doc/device-tree-bindings/i2c/ |
| D | i2c.txt | 19 Pin description for I2C bus software deblocking.
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| /external/u-boot/arch/arm/dts/ |
| D | keystone-k2l.dtsi | 106 /* Pin muxed. Enabled and configured by Bootloader */
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| D | armada-385-turris-omnia.dts | 381 /* Pin header CN10 */
388 /* Pin header CN11 */
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| D | rk3288-phycore-som.dtsi | 460 /* Pin for switching state between sleep and non-sleep state */
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| /external/u-boot/doc/device-tree-bindings/misc/ |
| D | intel-lpc.txt | 4 The device tree node which describes the operation of the Intel Low Pin
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| /external/u-boot/doc/device-tree-bindings/usb/ |
| D | dwc3-st.txt | 22 - pinctrl-0 : Pin control group
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| /external/u-boot/doc/ |
| D | README.m54418twr | 76 CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
77 CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
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| /external/u-boot/board/freescale/m547xevb/ |
| D | README | 86 CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
87 CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
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| /external/tensorflow/tensorflow/java/ |
| D | build_defs.bzl | 3 # Pin to Java 1.7 to ensure broader compatibility for the Java bindings on
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| /external/u-boot/board/freescale/m53017evb/ |
| D | README | 86 CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
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| /external/u-boot/board/freescale/m54455evb/ |
| D | README | 89 CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
90 CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
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| /external/u-boot/board/hisilicon/poplar/ |
| D | README | 19 JTAG 8-Pin JTAG
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| /external/adhd/scripts/audio_tuning/frontend/ |
| D | audio.js | 910 var p = new Pin();
916 function Pin(node, index) { class
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| /external/u-boot/board/sbc8548/ |
| D | README | 85 to R313 pin 2. Pin 2 for each resistor is the end of the
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| /external/u-boot/drivers/pinctrl/ |
| D | Kconfig | 5 menu "Pin controllers"
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| /external/u-boot/board/freescale/m5373evb/ |
| D | README | 85 CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
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| /external/llvm/lib/Target/X86/ |
| D | X86.td | 368 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
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