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Searched refs:PostIndex (Results 1 – 25 of 51) sorted by relevance

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/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-memop-immediate-512-a32.cc1600 {{al, r0, r2, minus, 180, PostIndex},
1605 {{al, r7, r10, plus, 36, PostIndex},
1615 {{al, r0, r8, plus, 182, PostIndex},
1630 {{al, r11, r3, minus, 116, PostIndex},
1640 {{al, r7, r1, plus, 13, PostIndex},
1650 {{al, r0, r4, plus, 135, PostIndex},
1660 {{al, r13, r6, plus, 211, PostIndex},
1665 {{al, r11, r8, plus, 32, PostIndex},
1675 {{al, r0, r13, minus, 79, PostIndex},
1685 {{al, r5, r10, plus, 91, PostIndex},
[all …]
Dtest-assembler-cond-rd-memop-immediate-8192-a32.cc1605 {{al, r7, r12, plus, 1804, PostIndex},
1615 {{al, r0, r8, minus, 4, PostIndex},
1620 {{al, r14, r2, plus, 1635, PostIndex},
1660 {{al, r13, r10, plus, 1459, PostIndex},
1665 {{al, r11, r12, plus, 2490, PostIndex},
1670 {{al, r7, r9, plus, 2026, PostIndex},
1705 {{al, r2, r0, minus, 1526, PostIndex},
1735 {{al, r6, r11, minus, 4095, PostIndex},
1740 {{al, r0, r2, plus, 459, PostIndex},
1760 {{al, r3, r13, plus, 342, PostIndex},
[all …]
Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc1612 {{al, r13, r3, minus, r1, ROR, 31, PostIndex},
1617 {{al, r9, r7, minus, r1, LSL, 8, PostIndex},
1647 {{al, r0, r14, plus, r2, LSL, 10, PostIndex},
1657 {{al, r0, r4, minus, r12, LSL, 31, PostIndex},
1662 {{al, r11, r12, plus, r7, LSL, 25, PostIndex},
1667 {{al, r2, r10, minus, r7, ROR, 22, PostIndex},
1682 {{al, r11, r5, plus, r3, ROR, 29, PostIndex},
1702 {{al, r5, r14, plus, r14, ROR, 15, PostIndex},
1717 {{al, r8, r7, plus, r6, ROR, 27, PostIndex},
1737 {{al, r7, r0, plus, r0, ROR, 23, PostIndex},
[all …]
Dtest-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc1612 {{al, r12, r11, minus, r8, LSR, 2, PostIndex},
1617 {{al, r9, r3, plus, r10, ASR, 28, PostIndex},
1627 {{al, r14, r11, minus, r2, ASR, 2, PostIndex},
1657 {{al, r0, r13, minus, r4, ASR, 26, PostIndex},
1667 {{al, r0, r4, minus, r8, ASR, 21, PostIndex},
1672 {{al, r11, r6, plus, r2, LSR, 31, PostIndex},
1677 {{al, r2, r9, minus, r2, LSR, 29, PostIndex},
1692 {{al, r11, r0, plus, r4, ASR, 18, PostIndex},
1712 {{al, r5, r11, minus, r11, LSR, 30, PostIndex},
1727 {{al, r8, r3, minus, r0, LSR, 10, PostIndex},
[all …]
Dtest-assembler-cond-rd-memop-rs-a32.cc1619 {{al, r9, r4, plus, r7, PostIndex},
1629 {{al, r5, r9, minus, r14, PostIndex},
1644 {{al, r14, r7, minus, r5, PostIndex},
1649 {{al, r1, r11, plus, r14, PostIndex},
1659 {{al, r1, r13, plus, r11, PostIndex},
1664 {{al, r6, r12, minus, r7, PostIndex},
1674 {{al, r2, r11, plus, r4, PostIndex},
1689 {{al, r1, r6, minus, r6, PostIndex},
1749 {{al, r9, r13, plus, r3, PostIndex},
1754 {{al, r7, r11, plus, r13, PostIndex},
[all …]
Dtest-simulator-cond-rd-memop-immediate-8192-a32.cc1328 {{al, r14, r11, plus, 1506, PostIndex},
1333 {{al, r7, r14, plus, 3399, PostIndex},
1338 {{al, r11, r6, plus, 2588, PostIndex},
1343 {{al, r4, r9, plus, 2906, PostIndex},
1348 {{al, r4, r8, plus, 1916, PostIndex},
1353 {{al, r6, r0, plus, 1835, PostIndex},
1358 {{al, r1, r14, plus, 2984, PostIndex},
1363 {{al, r9, r12, plus, 3994, PostIndex},
1368 {{al, r10, r5, plus, 766, PostIndex},
1373 {{al, r5, r9, plus, 188, PostIndex},
[all …]
Dtest-simulator-cond-rd-memop-immediate-512-a32.cc1328 {{al, r14, r7, plus, 211, PostIndex},
1333 {{al, r7, r11, plus, 202, PostIndex},
1338 {{al, r11, r3, plus, 175, PostIndex},
1343 {{al, r4, r8, plus, 129, PostIndex},
1348 {{al, r4, r7, plus, 71, PostIndex},
1353 {{al, r5, r12, plus, 226, PostIndex},
1358 {{al, r1, r14, plus, 53, PostIndex},
1363 {{al, r9, r10, plus, 116, PostIndex},
1368 {{al, r10, r2, plus, 137, PostIndex},
1373 {{al, r5, r7, plus, 157, PostIndex},
[all …]
Dtest-simulator-cond-rd-memop-rs-a32.cc1335 {{al, r8, r11, plus, r4, PostIndex},
1340 {{al, r4, r1, plus, r2, PostIndex},
1345 {{al, r0, r7, plus, r5, PostIndex},
1350 {{al, r3, r6, plus, r10, PostIndex},
1355 {{al, r7, r3, plus, r6, PostIndex},
1360 {{al, r14, r0, plus, r3, PostIndex},
1365 {{al, r11, r0, plus, r2, PostIndex},
1370 {{al, r11, r14, plus, r3, PostIndex},
1375 {{al, r10, r3, plus, r14, PostIndex},
1380 {{al, r3, r10, plus, r4, PostIndex},
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc1333 {{al, r9, r0, plus, r4, LSR, 26, PostIndex},
1338 {{al, r2, r1, plus, r9, LSR, 30, PostIndex},
1343 {{al, r11, r7, plus, r8, LSR, 13, PostIndex},
1348 {{al, r5, r11, plus, r3, ASR, 2, PostIndex},
1353 {{al, r5, r12, plus, r11, LSR, 27, PostIndex},
1358 {{al, r3, r1, plus, r9, ASR, 5, PostIndex},
1363 {{al, r12, r6, plus, r8, ASR, 9, PostIndex},
1368 {{al, r4, r12, plus, r8, ASR, 10, PostIndex},
1373 {{al, r4, r9, plus, r10, LSR, 7, PostIndex},
1378 {{al, r6, r7, plus, r3, LSR, 8, PostIndex},
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc1333 {{al, r9, r4, plus, r0, ROR, 19, PostIndex},
1338 {{al, r2, r3, plus, r8, LSL, 10, PostIndex},
1343 {{al, r11, r14, plus, r5, LSL, 31, PostIndex},
1348 {{al, r5, r14, plus, r9, ROR, 11, PostIndex},
1353 {{al, r6, r1, plus, r5, LSL, 11, PostIndex},
1358 {{al, r3, r2, plus, r14, LSL, 19, PostIndex},
1363 {{al, r12, r11, plus, r10, ROR, 6, PostIndex},
1368 {{al, r5, r0, plus, r10, LSL, 18, PostIndex},
1373 {{al, r4, r11, plus, r8, ROR, 6, PostIndex},
1378 {{al, r6, r9, plus, r14, ROR, 15, PostIndex},
[all …]
Dtest-disasm-a32.cc676 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PostIndex)), in TEST()
680 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xff123, PostIndex)), in TEST()
683 COMPARE_A32(Ldr(r0, MemOperand(r1, -0xff123, PostIndex)), in TEST()
687 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xfff12, PostIndex)), in TEST()
691 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xff12, PostIndex)), in TEST()
694 COMPARE_T32(Ldr(r0, MemOperand(r1, -0xff12, PostIndex)), in TEST()
724 MUST_FAIL_TEST_BOTH(Ldr(r0, MemOperand(r0, 0xfff12, PostIndex)), in TEST()
760 COMPARE_T32(Ldr(r0, MemOperand(r1, minus, r2, PostIndex)), in TEST()
774 COMPARE_A32(Ldr(pc, MemOperand(r0, r0, PostIndex)), "ldr pc, [r0], r0\n"); in TEST()
775 COMPARE_T32(Ldr(pc, MemOperand(r0, r0, PostIndex)), in TEST()
[all …]
/external/v8/src/arm/
Dcodegen-arm.cc75 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); in CreateMemCopyUint8Function()
79 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); in CreateMemCopyUint8Function()
81 __ vst1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(dest, PostIndex)); in CreateMemCopyUint8Function()
82 __ vst1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(dest, PostIndex)); in CreateMemCopyUint8Function()
87 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); in CreateMemCopyUint8Function()
88 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); in CreateMemCopyUint8Function()
90 __ vst1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(dest, PostIndex)); in CreateMemCopyUint8Function()
91 __ vst1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(dest, PostIndex)); in CreateMemCopyUint8Function()
92 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); in CreateMemCopyUint8Function()
93 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); in CreateMemCopyUint8Function()
[all …]
Dmacro-assembler-arm.h187 ldr(src2, MemOperand(sp, 4, PostIndex), cond);
188 ldr(src1, MemOperand(sp, 4, PostIndex), cond);
199 ldr(src3, MemOperand(sp, 4, PostIndex), cond);
204 ldr(src1, MemOperand(sp, 4, PostIndex), cond);
218 ldr(src4, MemOperand(sp, 4, PostIndex), cond);
227 ldr(src1, MemOperand(sp, 4, PostIndex), cond);
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc168 __ ldp(w23, w24, MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceBase()
171 __ ldp(x25, x26, MemOperand(x1, 16, PostIndex)); in GenerateTestSequenceBase()
174 __ ldpsw(x27, x28, MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceBase()
177 __ ldr(w29, MemOperand(x1, 4, PostIndex)); in GenerateTestSequenceBase()
180 __ ldr(x2, MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceBase()
183 __ ldrb(w3, MemOperand(x1, 1, PostIndex)); in GenerateTestSequenceBase()
186 __ ldrb(x4, MemOperand(x1, 1, PostIndex)); in GenerateTestSequenceBase()
189 __ ldrh(w5, MemOperand(x1, 2, PostIndex)); in GenerateTestSequenceBase()
192 __ ldrh(x6, MemOperand(x1, 2, PostIndex)); in GenerateTestSequenceBase()
195 __ ldrsb(w7, MemOperand(x1, 1, PostIndex)); in GenerateTestSequenceBase()
[all …]
Dtest-cpu-features-aarch64.cc287 TEST_NONE(ldpsw_1, ldpsw(x0, x1, MemOperand(x2, -36, PostIndex)))
290 TEST_NONE(ldp_1, ldp(w0, w1, MemOperand(x2, -212, PostIndex)))
293 TEST_NONE(ldp_4, ldp(x0, x1, MemOperand(x2, 8, PostIndex)))
295 TEST_NONE(ldrb_0, ldrb(w0, MemOperand(x1, -219, PostIndex)))
301 TEST_NONE(ldrh_0, ldrh(w0, MemOperand(x1, -135, PostIndex)))
306 TEST_NONE(ldrsb_0, ldrsb(w0, MemOperand(x1, 160, PostIndex)))
309 TEST_NONE(ldrsb_3, ldrsb(x0, MemOperand(x1, 33, PostIndex)))
318 TEST_NONE(ldrsh_0, ldrsh(w0, MemOperand(x1, 11, PostIndex)))
321 TEST_NONE(ldrsh_3, ldrsh(x0, MemOperand(x1, -78, PostIndex)))
328 TEST_NONE(ldrsw_0, ldrsw(x0, MemOperand(x1, 73, PostIndex)))
[all …]
Dtest-disasm-aarch64.cc1074 COMPARE(ldr(w0, MemOperand(x1, 4, PostIndex)), "ldr w0, [x1], #4"); in TEST()
1075 COMPARE(ldr(w2, MemOperand(x3, 255, PostIndex)), "ldr w2, [x3], #255"); in TEST()
1076 COMPARE(ldr(w4, MemOperand(x5, -256, PostIndex)), "ldr w4, [x5], #-256"); in TEST()
1077 COMPARE(ldr(x6, MemOperand(x7, 8, PostIndex)), "ldr x6, [x7], #8"); in TEST()
1078 COMPARE(ldr(x8, MemOperand(x9, 255, PostIndex)), "ldr x8, [x9], #255"); in TEST()
1079 COMPARE(ldr(x10, MemOperand(x11, -256, PostIndex)), "ldr x10, [x11], #-256"); in TEST()
1080 COMPARE(str(w12, MemOperand(x13, 4, PostIndex)), "str w12, [x13], #4"); in TEST()
1081 COMPARE(str(w14, MemOperand(x15, 255, PostIndex)), "str w14, [x15], #255"); in TEST()
1082 COMPARE(str(w16, MemOperand(x17, -256, PostIndex)), "str w16, [x17], #-256"); in TEST()
1083 COMPARE(str(x18, MemOperand(x19, 8, PostIndex)), "str x18, [x19], #8"); in TEST()
[all …]
Dtest-assembler-aarch64.cc3164 __ Ldr(w1, MemOperand(x24, 4096 * sizeof(src[0]), PostIndex)); in TEST()
3165 __ Str(w1, MemOperand(x25, 4096 * sizeof(dst[0]), PostIndex)); in TEST()
3266 __ Ldr(w0, MemOperand(x17, 4, PostIndex)); in TEST()
3267 __ Str(w0, MemOperand(x18, 12, PostIndex)); in TEST()
3268 __ Ldr(x1, MemOperand(x19, 8, PostIndex)); in TEST()
3269 __ Str(x1, MemOperand(x20, 16, PostIndex)); in TEST()
3270 __ Ldr(x2, MemOperand(x21, -8, PostIndex)); in TEST()
3271 __ Str(x2, MemOperand(x22, -32, PostIndex)); in TEST()
3272 __ Ldrb(w3, MemOperand(x23, 1, PostIndex)); in TEST()
3273 __ Strb(w3, MemOperand(x24, 5, PostIndex)); in TEST()
[all …]
/external/vixl/examples/aarch64/
Dadd2-vectors.cc57 __ Ld1(v1.V16B(), MemOperand(x1, 16, PostIndex)); in GenerateAdd2Vectors()
59 __ St1(v0.V16B(), MemOperand(x0, 16, PostIndex)); in GenerateAdd2Vectors()
72 __ Ldrb(w6, MemOperand(x1, 1, PostIndex)); in GenerateAdd2Vectors()
74 __ Strb(w5, MemOperand(x0, 1, PostIndex)); in GenerateAdd2Vectors()
Dsum-array.cc49 __ Ldrb(w3, MemOperand(x2, 1, PostIndex)); // w3 = *(x2++) in GenerateSumArray()
Dcrc-checksums.cc57 __ Ldrb(w3, MemOperand(x2, 1, PostIndex)); in GenerateCrc32()
/external/v8/src/regexp/arm64/
Dregexp-macro-assembler-arm64.cc248 __ Ldrb(w10, MemOperand(characters_address, 1, PostIndex)); in CheckCharacters()
251 __ Ldrh(w10, MemOperand(characters_address, 2, PostIndex)); in CheckCharacters()
329 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); in CheckNotBackReferenceIgnoreCase()
330 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); in CheckNotBackReferenceIgnoreCase()
481 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); in CheckNotBackReference()
482 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); in CheckNotBackReference()
485 __ Ldrh(w10, MemOperand(capture_start_address, 2, PostIndex)); in CheckNotBackReference()
486 __ Ldrh(w11, MemOperand(current_position_address, 2, PostIndex)); in CheckNotBackReference()
885 MemOperand(output_array(), kPointerSize, PostIndex)); in GetCode()
906 MemOperand(base, -kPointerSize, PostIndex)); in GetCode()
[all …]
/external/v8/src/regexp/arm/
Dregexp-macro-assembler-arm.cc252 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); in CheckNotBackReferenceIgnoreCase()
253 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); in CheckNotBackReferenceIgnoreCase()
387 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); in CheckNotBackReference()
388 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); in CheckNotBackReference()
391 __ ldrh(r3, MemOperand(r0, char_size(), PostIndex)); in CheckNotBackReference()
392 __ ldrh(r4, MemOperand(r2, char_size(), PostIndex)); in CheckNotBackReference()
767 __ str(r2, MemOperand(r0, kPointerSize, PostIndex)); in GetCode()
768 __ str(r3, MemOperand(r0, kPointerSize, PostIndex)); in GetCode()
1176 MemOperand(backtrack_stackpointer(), kPointerSize, PostIndex)); in Pop()
/external/vixl/src/aarch32/
Doperands-aarch32.cc520 if (operand.GetAddrMode() == PostIndex) { in operator <<()
552 if (operand.GetAddrMode() == PostIndex) { in operator <<()
Ddisasm-aarch32.cc10165 PostIndex)); in DecodeT32()
10625 PostIndex)); in DecodeT32()
10820 PostIndex)); in DecodeT32()
10938 PostIndex)); in DecodeT32()
11077 PostIndex)); in DecodeT32()
11295 PostIndex)); in DecodeT32()
11344 PostIndex)); in DecodeT32()
11399 PostIndex)); in DecodeT32()
11456 PostIndex)); in DecodeT32()
11509 PostIndex)); in DecodeT32()
[all …]
Dmacro-assembler-aarch32.cc1769 case PostIndex: in Delegate()
1783 MemOperand(rn, load_store_offset, PostIndex)); in Delegate()
1866 case PostIndex: in Delegate()
1995 case PostIndex: in Delegate()
2009 MemOperand(rn, load_store_offset, PostIndex)); in Delegate()
2042 case PostIndex: in Delegate()
2142 case PostIndex: in Delegate()
2215 case PostIndex: in Delegate()

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