| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 318 ICmpInst::Predicate &PredR) { in getMaskedTypeForICmpPair() argument
359 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) { in getMaskedTypeForICmpPair()
394 if (!ICmpInst::isEquality(PredR)) in getMaskedTypeForICmpPair()
436 unsigned RightType = getMaskedICmpType(A, D, E, PredR); in getMaskedTypeForICmpPair()
447 ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed() argument
478 if (PredR != NewCC) in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed()
577 ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, in foldLogOpOfMaskedICmpsAsymmetric() argument
580 assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) && in foldLogOpOfMaskedICmpsAsymmetric()
594 PredL, PredR, Builder)) { in foldLogOpOfMaskedICmpsAsymmetric()
600 PredR, PredL, Builder)) { in foldLogOpOfMaskedICmpsAsymmetric()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 126 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {} in FlowPattern()
132 unsigned PredR = 0; member
147 << ", PredR:" << printReg(P.FP.PredR, &P.TRI) in operator <<()
198 MachineInstr *MI, unsigned PredR, bool IfTrue);
201 unsigned PredR, bool IfTrue);
204 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
254 unsigned PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
334 FP = FlowPattern(B, PredR, TB, FB, JB); in matchFlowPattern()
711 unsigned PredR, bool IfTrue) { in predicateInstr() argument
729 MIB.addReg(PredR); in predicateInstr()
[all …]
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| D | HexagonGenMux.cpp | 93 unsigned PredR = 0; member
109 unsigned DefR, PredR; member
116 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
257 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
264 F->second.PredR = PR; in genMuxInBlock()
339 .addReg(MX.PredR) in genMuxInBlock()
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| D | HexagonExpandCondsets.cpp | 221 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
228 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
746 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
759 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI))) in getReachingDefForPred()
769 if (RR.Reg == PredR) { in getReachingDefForPred()
916 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
925 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))) in renameInRange()
965 unsigned PredR = MP.getReg(); in predicate() local
966 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
983 if (!I->modifiesRegister(PredR, nullptr)) in predicate()
[all …]
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| D | HexagonHardwareLoops.cpp | 462 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) in findInductionRegister()
466 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
1338 unsigned PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1346 if (MO.getReg() == PredR) // Found an intervening use of PredR. in orderBumpCompare()
1917 unsigned PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
1923 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
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| D | HexagonISelLowering.cpp | 287 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
288 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult()
294 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 106 FlowPattern() : SplitB(0), TrueB(0), FalseB(0), JoinB(0), PredR(0) {} in FlowPattern()
109 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {} in FlowPattern()
113 unsigned PredR; member
126 << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI) in operator <<()
174 MachineInstr *MI, unsigned PredR, bool IfTrue);
177 unsigned PredR, bool IfTrue);
227 unsigned PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
306 FP = FlowPattern(B, PredR, TB, FB, JB); in matchFlowPattern()
708 unsigned PredR, bool IfTrue) { in predicateInstr() argument
721 .addReg(PredR); in predicateInstr()
[all …]
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| D | HexagonGenMux.cpp | 62 unsigned PredR; member
64 CondsetInfo() : PredR(0), TrueX(UINT_MAX), FalseX(UINT_MAX) {} in CondsetInfo()
73 unsigned DefR, PredR; member
79 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
220 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
227 F->second.PredR = PR; in genMuxInBlock()
300 .addReg(MX.PredR) in genMuxInBlock()
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| D | HexagonExpandCondsets.cpp | 258 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
265 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
743 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
756 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI))) in getReachingDefForPred()
766 if (RR.Reg == PredR) { in getReachingDefForPred()
917 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
926 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))) in renameInRange()
967 unsigned PredR = MP.getReg(); in predicate() local
968 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
985 if (!I->modifiesRegister(PredR, 0)) in predicate()
[all …]
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| D | HexagonHardwareLoops.cpp | 443 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
444 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) in findInductionRegister()
447 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
1298 unsigned PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1306 if (MO.getReg() == PredR) // Found an intervening use of PredR. in orderBumpCompare()
1877 unsigned PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
1883 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
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| D | HexagonBitSimplify.cpp | 2692 unsigned PredR = 0; in processLoop() local
2693 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PredR)) { in processLoop()
2704 PredR = MRI->createVirtualRegister(RC); in processLoop()
2709 BuildMI(*C.PB, T, DL, HII->get(TfrI), PredR) in processLoop()
2712 PredR = F->PR.Reg; in processLoop()
2715 assert(MRI->getRegClass(PredR) == MRI->getRegClass(G.Inp.Reg)); in processLoop()
2716 moveGroup(G, *F->LB, *F->PB, F->LB->getFirstNonPHI(), F->DefR, PredR); in processLoop()
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| D | HexagonISelLowering.cpp | 636 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
637 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult()
640 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1, in LowerCallResult()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 1703 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in simplifyAndOrOfFCmps() local
1704 if ((PredL == FCmpInst::FCMP_ORD && PredR == FCmpInst::FCMP_ORD && IsAnd) || in simplifyAndOrOfFCmps()
1705 (PredL == FCmpInst::FCMP_UNO && PredR == FCmpInst::FCMP_UNO && !IsAnd)) { in simplifyAndOrOfFCmps()
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