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/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_amd64.s65 MOVQ mlen+16(FP), R15
76 CMPQ R15, $16
84 SUBQ $16, R15
85 CMPQ R15, $16
89 TESTQ R15, R15
94 ADDQ R15, SI
102 DECQ R15
108 MOVQ $16, R15
/external/boringssl/src/ssl/test/runner/curve25519/
Dladderstep_amd64.s74 MOVQ DX,R15
88 ADCQ DX,R15
97 ADCQ DX,R15
135 SHLQ $13,R15:R14
138 IMUL3Q $19,R15,CX
189 MOVQ DX,R15
203 ADCQ DX,R15
212 ADCQ DX,R15
250 SHLQ $13,R15:R14
253 IMUL3Q $19,R15,CX
[all …]
Dsquare_amd64.s39 MOVQ AX,R15
53 ADDQ AX,R15
62 ADDQ AX,R15
101 SHLQ $13,BX:R15
102 ANDQ SI,R15
103 ADDQ R14,R15
120 ADDQ R15,DX
Dmul_amd64.s46 MOVQ DX,R15
62 ADCQ DX,R15
79 ADCQ DX,R15
97 ADCQ DX,R15
125 ADCQ DX,R15
135 SHLQ $13,R15:R14
140 ADDQ R15,BX
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll97 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
98 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
128 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
129 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
160 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
161 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
189 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
190 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
220 ; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
221 ; CHECK: sc $[[R15]], 0($[[R2]])
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaFrameLowering.cpp96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); in emitPrologue()
98 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) in emitEpilogue()
124 .addReg(Alpha::R15); in emitEpilogue()
126 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) in emitEpilogue()
127 .addImm(0).addReg(Alpha::R15); in emitEpilogue()
DAlphaRegisterInfo.cpp73 Reserved.set(Alpha::R15); in getReservedRegs()
149 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); in eliminateFrameIndex()
172 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); in eliminateFrameIndex()
182 return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30; in getFrameRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dipra-local-linkage.ll7 ; When IPRA is not enabled R15 will be saved by foo as it is callee saved reg.
20 ; As R15 is clobbered by foo() when IPRA is enabled value of R15 should be
/external/llvm/test/CodeGen/X86/
Dipra-local-linkage.ll7 ; When IPRA is not enabled R15 will be saved by foo as it is callee saved reg.
20 ; As R15 is clobbered by foo() when IPRA is enabled value of R15 should be
/external/llvm/test/CodeGen/Mips/
Datomic.ll152 ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
153 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
197 ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
198 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
242 ; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]]
244 ; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]]
290 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
291 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
332 ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
333 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td38 def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
50 R15, RCA, // register for constant addresses
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td38 def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
50 R15, RCA, // register for constant addresses
/external/syzkaller/pkg/report/testdata/linux/report/
D14224 [ 95.884349] R13: 1ffff1003b680fd4 R14: ffff8801cee560c0 R15: ffff8801db407fc0
44 [ 95.884470] R13: ffff8801db12d500 R14: ffff8801d86b85a0 R15: ffffffff85ec8220
73 [ 95.884736] R13: 00000000ffffffff R14: 00007f6b9af6b6d4 R15: 0000000000000000
D451 [ 56.197865] R13: ffff8801c52be780 R14: ffff8801c65be600 R15: ffff8801c6358d40
94 [ 56.396328] R13: 00000000ffffffff R14: 0000000020000000 R15: 0000000000ffa000
123 R13: ffff8801c52be780 R14: ffff8801c65be600 R15: ffff8801c6358d40
134 R13: 00000000ffffffff R14: 0000000020000000 R15: 0000000000ffa000
D16023 [ 190.757101] R13: ffffffff885293b0 R14: 0000000000000000 R15: ffff88021fd19b48
47 [ 190.757101] R13: 00000000f780000e R14: ffff8801aa907120 R15: 0000000000000000
103 [ 190.757101] R13: 00000000ffffffff R14: 00007f80206db6d4 R15: 0000000000000000
D6718 [ 562.834404] R13: ffff8801bf6677d8 R14: dffffc0000000000 R15: ffffc9000137ba06
75 [ 563.114524] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000
118 [ 563.337911] R13: ffff8801bf6677d8 R14: dffffc0000000000 R15: ffffc9000137ba06
169 [ 563.579660] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000
D22967 [ 212.857972] R13: 0000000000000662 R14: 00000000006fc9d0 R15: 0000000000000003
98 [ 213.009683] R13: ffff8801be761000 R14: 00000000014080c0 R15: ffff88018cf8c400
145 [ 213.224824] R13: 0000000000000662 R14: 00000000006fc9d0 R15: 0000000000000000
186 [ 213.423363] R13: 0000000000000662 R14: 00000000006fc9d0 R15: 0000000000000004
D25616 [ 27.471838] R13: ffff8801afb4fc00 R14: ffff8801d96f3812 R15: ffff8801d96f3c58
96 [ 27.862059] R13: 0000000000401680 R14: 0000000000000000 R15: 0000000000000000
109 [ 27.930483] R13: ffff8801afb4fc00 R14: ffff8801d96f3812 R15: ffff8801d96f3c58
D22847 [ 177.158181] R13: 00000000000004f7 R14: 00000000006fa7c8 R15: 0000000000000000
92 [ 177.347158] R13: 00000000000004f7 R14: 00000000006fa7c8 R15: 0000000000000000
121 R13: 00000000000004f7 R14: 00000000006fa7c8 R15: 0000000000000000
D17518 [ 83.543161] R13: ffffc90000f13f28 R14: ffff8801fd2dec00 R15: 0000000000000068
32 [ 83.625533] R13: 00000000ffffffff R14: 00007fd1a2fd16d4 R15: 0000000000000000
D11424 [ 161.631508] R13: 0000000000000000 R14: ffff8801c7edf948 R15: ffff8801c7edf8b0
40 [ 161.632035] R13: 00000000ffffffff R14: 00007ff14d1796d4 R15: 0000000000000000
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td46 def R15 : Core<15, "%r15">, DwarfRegNum<[15]>;
73 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
79 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
/external/llvm/lib/Target/MSP430/
DMSP430CallingConv.td19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/
DMSP430CallingConv.td19 // i16 are returned in registers R12, R13, R14, R15
20 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp86 case X86::ESI: case X86::R15: return 5; in getCompactUnwindRegNum()
104 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: in getSEHRegNum()
361 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
366 X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
371 X86::R12, X86::R13, X86::R14, X86::R15, in getCalleeSavedRegs()
433 X86::R12, X86::R13, X86::R14, X86::R15 in getReservedRegs()
711 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
748 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
784 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
820 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
[all …]

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