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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/
Dzext.ll3 ; zext R25:R24, R24
12 ; zext R25:R24, R20
13 ; mov R24, R20
23 ; zext R25:R24, R24
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRCallingConv.td18 // i8 is returned in R24.
19 CCIfType<[i8], CCAssignToReg<[R24]>>,
21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
28 CCIfType<[i8], CCAssignToReg<[R24,R25]>>,
49 CCIfType<[i8], CCAssignToReg<[R24,R22]>>,
DAVRRegisterInfo.td69 def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>;
94 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>;
117 add R24, R25, R18, R19, R20, R21, R22, R23,
135 add R24, R25, R18, R19, R20, R21, R22, R23,
/external/llvm/lib/Target/AVR/
DAVRCallingConv.td18 // i8 is returned in R24.
19 CCIfType<[i8], CCAssignToReg<[R24]>>,
21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
28 CCIfType<[i8], CCAssignToReg<[R24,R25]>>,
56 CCIfType<[i8], CCAssignToReg<[R24,R22]>>,
DAVRRegisterInfo.td69 def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>;
94 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
/external/boringssl/src/crypto/poly1305/
Dpoly1305_vec.c65 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member
120 p->R24.d[1] = U8TO32_LE(key + 24); in CRYPTO_poly1305_init()
121 p->R24.d[3] = U8TO32_LE(key + 28); in CRYPTO_poly1305_init()
155 pad1 = ((uint64_t)p->R24.d[3] << 32) | (uint64_t)p->R24.d[1]; in poly1305_first_block()
192 p->R24.v = _mm_shuffle_epi32(_mm_cvtsi32_si128((uint32_t)((r22 >> 16))), in poly1305_first_block()
197 p->S24.v = _mm_mul_epu32(p->R24.v, FIVE); in poly1305_first_block()
211 p->R24.d[1] = (uint32_t)(pad1); in poly1305_first_block()
212 p->R24.d[3] = (uint32_t)(pad1 >> 32); in poly1305_first_block()
252 T4 = _mm_mul_epu32(H0, p->R24.v); in poly1305_blocks()
347 T5 = _mm_mul_epu32(M0, p->R24.v); in poly1305_blocks()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h129 case MBlaze::R24 : return 24; in getMBlazeRegisterNumbering()
194 case 24 : return MBlaze::R24; in getMBlazeRegisterFromNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td27 R21, R22, R23, R24, R25, R26, R27, R28, R29,
44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dtwo-extenders.s112 {R24 = #1; memw(##0x1000) = R24.new}
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td57 def R24 : Core<24, "%r24">, DwarfRegNum<[24]>;
74 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h161 {PPC::R24, -32}, in getCalleeSavedSpillSlots()
240 {PPC::R24, -60}, in getCalleeSavedSpillSlots()
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp109 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
118 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
DHexagonFrameLowering.h67 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 }, in getCalleeSavedSpillSlots()
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h98 case Lanai::R24: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h98 case Lanai::R24: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaRegisterInfo.td62 def R24 : GPR<24, "$24">, DwarfRegNum<[24]>;
116 R23, R24, R25, R28,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h55 case R24: case X24: case F24: case V24: case CR6LT: return 24; in getPPCRegisterNumbering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp107 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
116 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
DHexagonFrameLowering.h90 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 }, in getCalleeSavedSpillSlots()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.cpp62 MBlaze::R24, MBlaze::R25, MBlaze::R26, MBlaze::R27, in getCalleeSavedRegs()
DMBlazeRegisterInfo.td66 def R24 : MBlazeGPRReg< 24, "r24">, DwarfRegNum<[24]>;
/external/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp158 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td223 R21, R22, R23, R24, R25, R26, R27, R28,
232 R21, R22, R23, R24, R25, R26, R27, R28,
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp170 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,

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