Home
last modified time | relevance | path

Searched refs:RA (Results 1 – 25 of 766) sorted by relevance

12345678910>>...31

/external/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td18 bits<5> RA;
24 let Inst{11-15} = RA;
37 bits<5> RA;
44 let Inst{11-15} = RA;
111 def EVMRA : EVXForm_1<1220, (outs gprc:$RT), (ins gprc:$RA),
112 "evmra $RT, $RA", IIC_VecFP> {
116 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
117 "brinc $RT, $RA, $RB", IIC_VecFP>;
118 def EVABS : EVXForm_2<520, (outs gprc:$RT), (ins gprc:$RA),
119 "evabs $RT, $RA", IIC_VecFP>;
[all …]
Dp9-instrs.txt63 [PO BF / L RA RB XO /] cmprb BF,L,RA,RB
66 [PO BF // RA RB XO /] cmpeqb BF,RA,RB
71 [PO RS RA /// XO Rc] cnttzw(.) RA,RS
76 [PO RS RA /// XO Rc] cnttzd(.) RA,RS
81 [PO /// L RA RB XO /] copy RA,RB,L
82 copy_first = copy RA, RB, 1
87 [PO /// L RA RB XO Rc] paste(.) RA,RB,L
88 paste_last = paste RA,RB,1
96 [PO RT RA RB RC XO] maddhd RT,RA.RB,RC
99 [PO RT RA RB RC XO] maddhdu RT,RA.RB,RC
[all …]
DPPCInstrHTM.td109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
113 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
119 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
124 def : Pat<(int_ppc_treclaim i32:$RA),
125 (TRECLAIM $RA)>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td19 bits<5> RA;
25 let Inst{11-15} = RA;
39 let RA = 0;
46 bits<5> RA;
51 let Inst{11-15} = RA;
60 bits<5> RA;
66 let Inst{11-15} = RA;
80 let RA = 0;
87 bits<5> RA;
94 let Inst{11-15} = RA;
[all …]
DPPCInstrHTM.td109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
113 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
119 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
124 def : Pat<(int_ppc_treclaim i32:$RA),
125 (TRECLAIM $RA)>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dcmpxchg-clobber-flags.ll2 …iple=i386-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=32-ALL,32-GOOD-RA
3 …386-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=32-…
5 …le=x86_64-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA
6 …_64-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-…
7 …u -verify-machineinstrs -mattr=+sahf %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF
8 … -verify-machineinstrs -mattr=+sahf -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-…
9 …u -verify-machineinstrs -mcpu=corei7 %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF
27 ; 32-GOOD-RA-LABEL: test_intervening_call:
28 ; 32-GOOD-RA: # %bb.0: # %entry
29 ; 32-GOOD-RA-NEXT: pushl %ebx
[all …]
Dvirtual-registers-cleared-in-machine-functions-liveins.ll1 …e=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA
2 …riple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA
13 ; PRE-RA: liveins:
14 ; PRE-RA-NEXT: - { reg: '$edi', virtual-reg: '%0' }
15 ; PRE-RA-NEXT: - { reg: '$esi', virtual-reg: '%1' }
17 ; POST-RA: liveins:
18 ; POST-RA-NEXT: - { reg: '$edi', virtual-reg: '' }
19 ; POST-RA-NEXT: - { reg: '$esi', virtual-reg: '' }
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaInstrInfo.td228 def Lr : OForm< opc, funl, !strconcat(asmstr, "l $RA,$RB,$RC"),
229 [(set GPRC:$RC, (intop (OpNode GPRC:$RA, GPRC:$RB)))], itin>;
230 def Li : OFormL<opc, funl, !strconcat(asmstr, "l $RA,$L,$RC"),
231 [(set GPRC:$RC, (intop (OpNode GPRC:$RA, immUExt8:$L)))], itin>;
232 def Qr : OForm< opc, funq, !strconcat(asmstr, "q $RA,$RB,$RC"),
233 [(set GPRC:$RC, (OpNode GPRC:$RA, GPRC:$RB))], itin>;
234 def Qi : OFormL<opc, funq, !strconcat(asmstr, "q $RA,$L,$RC"),
235 [(set GPRC:$RC, (OpNode GPRC:$RA, immUExt8:$L))], itin>;
246 def : Pat<(intop (add GPRC:$RA, immUExt8neg:$L)), (SUBLi GPRC:$RA, immUExt8neg:$L)>;
247 def : Pat<(add GPRC:$RA, immUExt8neg:$L), (SUBQi GPRC:$RA, immUExt8neg:$L)>;
[all …]
/external/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp77 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) { in scanInstr()
78 if (!LiveNodes.count(RA.Id)) in scanInstr()
79 WorkQ.push_back(RA.Id); in scanInstr()
124 auto RA = DFG.addr<RefNode*>(N); in collect() local
125 if (DFG.IsDef(RA)) in collect()
126 processDef(RA, WorkQ); in collect()
128 processUse(RA, WorkQ); in collect()
134 auto RA = DFG.addr<RefNode*>(N); in collect() local
135 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n"; in collect()
148 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) in collect()
[all …]
DRDFGraph.cpp87 void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA, in printRefHeader() argument
89 OS << Print<NodeId>(RA.Id, G) << '<' in printRefHeader()
90 << Print<RegisterRef>(RA.Addr->getRegRef(), G) << '>'; in printRefHeader()
91 if (RA.Addr->getFlags() & NodeAttrs::Fixed) in printRefHeader()
573 bool RegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { in covers() argument
574 if (RA == RB) in covers()
576 if (TargetRegisterInfo::isVirtualRegister(RA.Reg)) { in covers()
578 if (RA.Reg != RB.Reg) in covers()
580 if (RA.Sub == 0) in covers()
582 return TRI.composeSubRegIndices(RA.Sub, RB.Sub) == RA.Sub; in covers()
[all …]
DHexagonRDF.cpp19 bool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { in covers() argument
20 if (RA == RB) in covers()
23 if (TargetRegisterInfo::isVirtualRegister(RA.Reg) && in covers()
26 if (RA.Reg == RB.Reg) { in covers()
27 if (RA.Sub == 0) in covers()
34 return RegisterAliasInfo::covers(RA, RB); in covers()
DHexagonRDFOpt.cpp150 for (NodeAddr<RefNode*> RA : SA.Addr->members(DFG)) { in run()
151 R2I.insert(std::make_pair(RA.Id, SA.Id)); in run()
152 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
186 for (NodeAddr<RefNode*> RA : Refs) in removeOperand()
187 OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp()))); in removeOperand()
191 for (NodeAddr<RefNode*> RA : Refs) { in removeOperand()
192 unsigned N = OpMap[RA.Id]; in removeOperand()
194 RA.Addr->setRegRef(&MI->getOperand(N)); in removeOperand()
196 RA.Addr->setRegRef(&MI->getOperand(N-1)); in removeOperand()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp88 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) { in scanInstr()
89 if (!LiveNodes.count(RA.Id)) in scanInstr()
90 WorkQ.push_back(RA.Id); in scanInstr()
135 auto RA = DFG.addr<RefNode*>(N); in collect() local
136 if (DFG.IsDef(RA)) in collect()
137 processDef(RA, WorkQ); in collect()
139 processUse(RA, WorkQ); in collect()
145 auto RA = DFG.addr<RefNode*>(N); in collect() local
146 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n"; in collect()
159 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) in collect()
[all …]
DRDFGraph.cpp111 static void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA, in printRefHeader() argument
113 OS << Print<NodeId>(RA.Id, G) << '<' in printRefHeader()
114 << Print<RegisterRef>(RA.Addr->getRegRef(G), G) << '>'; in printRefHeader()
115 if (RA.Addr->getFlags() & NodeAttrs::Fixed) in printRefHeader()
811 NodeAddr<RefNode*> RA = NA; in cloneNode() local
812 RA.Addr->setReachingDef(0); in cloneNode()
813 RA.Addr->setSibling(0); in cloneNode()
909 for (NodeAddr<RefNode*> RA : IA.Addr->members(*this)) in build()
910 AllRefs.insert(RA.Addr->getRegRef(*this)); in build()
1148 NodeAddr<RefNode*> RA) const { in getRelatedRefs()
[all …]
DRDFRegisters.h116 bool alias(RegisterRef RA, RegisterRef RB) const { in alias()
117 if (!isRegMaskId(RA.Reg)) in alias()
118 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); in alias()
119 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); in alias()
153 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
167 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf()
169 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); in isCoverOf()
DHexagonRDFOpt.cpp166 for (NodeAddr<RefNode*> RA : SA.Addr->members(DFG)) { in run()
167 R2I.insert(std::make_pair(RA.Id, SA.Id)); in run()
168 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
201 for (NodeAddr<RefNode*> RA : Refs) in removeOperand()
202 OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp()))); in removeOperand()
206 for (NodeAddr<RefNode*> RA : Refs) { in removeOperand()
207 unsigned N = OpMap[RA.Id]; in removeOperand()
209 RA.Addr->setRegRef(&MI->getOperand(N), DFG); in removeOperand()
211 RA.Addr->setRegRef(&MI->getOperand(N-1), DFG); in removeOperand()
/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dinstructions.h9 #define __COPY(RA, RB, L) \ argument
10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
11 #define COPY(RA, RB, L) \ argument
12 .long __COPY((RA), (RB), (L))
33 #define __PASTE(RA, RB, L, RC) \ argument
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
35 #define PASTE(RA, RB, L, RC) \ argument
36 .long __PASTE((RA), (RB), (L), (RC))
/external/llvm/test/CodeGen/X86/
Dvirtual-registers-cleared-in-machine-functions-liveins.ll1 …e=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA
2 …riple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA
13 ; PRE-RA: liveins:
14 ; PRE-RA-NEXT: - { reg: '%edi', virtual-reg: '%0' }
15 ; PRE-RA-NEXT: - { reg: '%esi', virtual-reg: '%1' }
17 ; POST-RA: liveins:
18 ; POST-RA-NEXT: - { reg: '%edi' }
19 ; POST-RA-NEXT: - { reg: '%esi' }
/external/clang/test/Layout/
Dms-x86-alias-avoidance-padding.cpp301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp526 unsigned RA = getRA(insn); in getInstruction() local
536 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction()
540 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
544 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction()
547 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
562 if (RA == UNSUPPORTED) in getInstruction()
565 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
578 if (RD == UNSUPPORTED || RA == UNSUPPORTED) in getInstruction()
581 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
595 if (RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction()
[all …]
/external/tcpdump/tests/
Dieee802.11_exthdr.out2 …b/s 2412 MHz 11b -19dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment RA:90:a4:de:c0:46:0a
5 …b/s 2412 MHz 11b -18dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment RA:90:a4:de:c0:46:0a
8 …b/s 2412 MHz 11b -46dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment RA:90:a4:de:c0:46:0a
11 …b/s 2412 MHz 11b -57dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment RA:90:a4:de:c0:46:0a
14 …b/s 2412 MHz 11b -73dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment RA:90:a4:de:c0:46:0a
17 …b/s 2412 MHz 11b -74dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment RA:90:a4:de:c0:46:0a
20 …b/s 2412 MHz 11b -17dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment RA:90:a4:de:c0:46:0a
23 …b/s 2412 MHz 11b -18dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment RA:90:a4:de:c0:46:0a
/external/linux-kselftest/tools/testing/selftests/powerpc/context_switch/
Dcp_abort.c36 #define PASTE(RA, RB, L, RC) \ argument
37 .long (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
53 #define COPY(RA, RB, L) \ argument
54 .long (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUInstrFormats.td32 bits<7> RA;
40 let Inst{18-24} = RA;
51 let RA = 0 in {
52 // RR Format, where RA and RB are zeroed (dont care):
75 bits<7> RA;
85 let Inst{18-24} = RA;
95 bits<7> RA;
102 let Inst{18-24} = RA;
111 bits<7> RA;
118 let Inst{18-24} = RA;
[all …]
/external/swiftshader/third_party/LLVM/utils/TableGen/
DARMDecoderEmitter.cpp515 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
1086 void ARMFilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, in reportRegion() argument
1088 if (RA == ATTR_MIXED && AllowMixed) in reportRegion()
1090 else if (RA == ATTR_ALL_SET && !AllowMixed) in reportRegion()
1209 bitAttr_t RA = ATTR_NONE; in filterProcessor() local
1217 switch (RA) { in filterProcessor()
1224 RA = ATTR_ALL_SET; in filterProcessor()
1230 RA = ATTR_MIXED; in filterProcessor()
1239 reportRegion(RA, StartBit, BitIndex, AllowMixed); in filterProcessor()
1240 RA = ATTR_NONE; in filterProcessor()
[all …]
DFixedLenDecoderEmitter.cpp353 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
922 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, in reportRegion() argument
924 if (RA == ATTR_MIXED && AllowMixed) in reportRegion()
926 else if (RA == ATTR_ALL_SET && !AllowMixed) in reportRegion()
1045 bitAttr_t RA = ATTR_NONE; in filterProcessor() local
1053 switch (RA) { in filterProcessor()
1060 RA = ATTR_ALL_SET; in filterProcessor()
1066 RA = ATTR_MIXED; in filterProcessor()
1075 reportRegion(RA, StartBit, BitIndex, AllowMixed); in filterProcessor()
1076 RA = ATTR_NONE; in filterProcessor()
[all …]

12345678910>>...31