| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | bit-reverse-to-rbit.ll | 5 …UN: opt -instcombine -S < %s | llc -mtriple=armv7--linux-gnueabi | FileCheck %s --check-prefix=RBIT
6 …: opt -instcombine -S < %s | llc -mtriple=thumbv8--linux-gnueabi | FileCheck %s --check-prefix=RBIT
9 ;RBIT: rbit
|
| /external/llvm/test/CodeGen/ARM/ |
| D | bit-reverse-to-rbit.ll | 5 …UN: opt -instcombine -S < %s | llc -mtriple=armv7--linux-gnueabi | FileCheck %s --check-prefix=RBIT
6 …: opt -instcombine -S < %s | llc -mtriple=thumbv8--linux-gnueabi | FileCheck %s --check-prefix=RBIT
9 ;RBIT: rbit
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-a32.json | 30 "Rbit", // RBIT{<c>}{<q>} <Rd>, <Rm> ; A1
|
| D | cond-rd-rn-t32.json | 34 "Rbit", // RBIT{<c>}{<q>} <Rd>, <Rm> ; T1
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 63 RBIT, // ARM bitreverse instruction enumerator
|
| D | ARMScheduleA9.td | 112 // CLZ, RBIT, etc.
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1022 RBIT = DataProcessing1SourceFixed | 0x00000000, enumerator
1023 RBIT_w = RBIT,
1024 RBIT_x = RBIT | SixtyFourBits,
|
| D | disasm-arm64.cc | 580 FORMAT(RBIT, "rbit"); in VisitDataProcessing1Source()
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1174 RBIT = DataProcessing1SourceFixed | 0x00000000, enumerator
1175 RBIT_w = RBIT,
1176 RBIT_x = RBIT | SixtyFourBits,
|
| D | disasm-aarch64.cc | 710 FORMAT(RBIT, "rbit"); in VisitDataProcessing1Source()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 148 // CLS,CLZ,RBIT,REV,REV16,REV32
498 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 150 // CLS,CLZ,RBIT,REV,REV16,REV32
500 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| D | AArch64SchedFalkorDetails.td | 923 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>;
945 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>;
1208 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
|
| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 41 // RBIT
|
| D | IntrinsicsARM.td | 159 // RBIT
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 132 // CLZ,RBIT,REV,REV16,REVSH,PKH
|
| D | ARMScheduleR52.td | 339 (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX")>;
|
| D | ARMScheduleA9.td | 116 // CLZ, RBIT, etc.
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 129 // CLZ,RBIT,REV,REV16,REVSH,PKH
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 927 ### RBIT ### subsection
2735 ### RBIT ### subsection
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1074 # RBIT
|
| D | thumb2.txt | 1293 # RBIT
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 962 def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1191 # RBIT
|
| D | thumb2.txt | 1432 # RBIT
|