| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-t32.json | 37 "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; T1
38 // REV16{<c>}{<q>} <Rd>, <Rm> ; T2
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| D | cond-rd-rn-a32.json | 32 "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; A1
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 333 # REV/REV16/REVSH
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| D | basic-arm-instructions.txt | 1084 # REV/REV16/REVSH
|
| D | thumb2.txt | 1321 # REV16
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 342 # REV/REV16/REVSH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 342 # REV/REV16/REVSH
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1025 REV16 = DataProcessing1SourceFixed | 0x00000400, enumerator
1026 REV16_w = REV16,
1027 REV16_x = REV16 | SixtyFourBits,
|
| D | disasm-arm64.cc | 581 FORMAT(REV16, "rev16"); in VisitDataProcessing1Source()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 107 REV16, enumerator
|
| D | AArch64SchedCyclone.td | 148 // CLS,CLZ,RBIT,REV,REV16,REV32
498 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 421 @ REV/REV16/REVSH
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 66 ; 64-bit REV16 is *not* a swap then a 16-bit rotation:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 66 ; 64-bit REV16 is *not* a swap then a 16-bit rotation:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 107 REV16, enumerator
|
| D | AArch64SchedCyclone.td | 150 // CLS,CLZ,RBIT,REV,REV16,REV32
500 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| D | AArch64SchedFalkorDetails.td | 1208 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1177 REV16 = DataProcessing1SourceFixed | 0x00000400, enumerator
1178 REV16_w = REV16,
1179 REV16_x = REV16 | SixtyFourBits,
|
| D | disasm-aarch64.cc | 711 FORMAT(REV16, "rev16"); in VisitDataProcessing1Source()
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 472 @ REV/REV16/REVSH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 472 @ REV/REV16/REVSH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 132 // CLZ,RBIT,REV,REV16,REVSH,PKH
|
| D | ARMScheduleR52.td | 339 (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX")>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 129 // CLZ,RBIT,REV,REV16,REVSH,PKH
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 948 ### REV16 ### subsection
2742 ### REV16 ### subsection
|