| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 54 case RRX: in IsValidAmount()
430 case RRX: in GetName()
594 if (amount_value == 0) SetType(RRX); in ImmediateShiftOperand()
735 case RRX: in AmountEncodingValue()
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| D | operands-aarch32.h | 111 case RRX: in Operand()
883 case RRX: in CheckShift()
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| D | instructions-aarch32.h | 1051 enum ShiftType { LSL = 0x0, LSR = 0x1, ASR = 0x2, ROR = 0x3, RRX = 0x4 }; enumerator
1066 bool IsRRX() const { return shift_ == RRX; } in IsRRX()
1102 case RRX: in ImmediateShiftOperand()
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| D | disasm-aarch32.cc | 18166 Operand(Register(rm), RRX)); in DecodeT32()
18232 Operand(Register(rm), RRX)); in DecodeT32()
18492 Operand(Register(rm), RRX)); in DecodeT32()
18564 Operand(Register(rm), RRX)); in DecodeT32()
18629 Operand(Register(rm), RRX)); in DecodeT32()
18686 Operand(Register(rm), RRX)); in DecodeT32()
18748 Operand(Register(rm), RRX)); in DecodeT32()
18819 Operand(Register(rm), RRX)); in DecodeT32()
19066 Operand(Register(rm), RRX)); in DecodeT32()
19138 Operand(Register(rm), RRX)); in DecodeT32()
[all …]
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| D | macro-assembler-aarch32.cc | 713 case RRX: in Delegate()
831 case RRX: in Delegate()
1027 case RRX: in Delegate()
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| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| D | mov-reg.ll | 2 ; are pseudo instructions for ASR, LSR, ROR, and RRX.
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| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-pc-a32.json | 29 "Rrx" // RRX{<c>}{<q>} {<Rd>}, <Rm> ; A1
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| D | cond-rd-rn-a32.json | 34 "Rrx", // RRX{<c>}{<q>} {<Rd>}, <Rm> ; A1
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| D | cond-rd-rn-t32.json | 41 "Rrx", // RRX{<c>}{<q>} {<Rd>}, <Rm> ; T3
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| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 248 __ Adc(r9, r2, Operand(r3, RRX)); in TEST()
276 __ Adc(r10, r2, Operand(r3, RRX)); in TEST()
371 __ Adcs(r3, r2, Operand(r1, RRX)); in TEST()
386 __ Adcs(r3, r2, Operand(r1, RRX)); in TEST()
487 __ Add(r9, r3, Operand(r1, RRX)); in TEST()
491 __ Add(r10, r3, Operand(r1, RRX)); in TEST()
524 __ And(r9, r1, Operand(r1, RRX)); in TEST()
528 __ And(r10, r1, Operand(r1, RRX)); in TEST()
613 __ Ands(r2, r0, Operand(r1, RRX)); in TEST()
628 __ Ands(r2, r0, Operand(r1, RRX)); in TEST()
[all …]
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.def | 100 X(RRX, "rrx")
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| /external/v8/src/arm/ |
| D | constants-arm.h | 246 RRX = -1, enumerator
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| D | assembler-arm.cc | 387 } else if (shift_op == RRX) { in Operand()
397 DCHECK(shift_op != RRX); in Operand()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 72 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. enumerator
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| D | ARMCodeEmitter.cpp | 808 case ARM::RRX: in emitPseudoMoveInstruction()
911 case ARM::RRX: in emitPseudoInstruction()
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| D | ARMExpandPseudoInsts.cpp | 869 case ARM::RRX: { in ExpandMI()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. enumerator
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| D | ARMScheduleSwift.td | 150 // ASR,LSL,ROR,RRX
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| D | ARMExpandPseudoInsts.cpp | 1214 case ARM::RRX: { in ExpandMI()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 96 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. enumerator
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| D | ARMScheduleA57.td | 228 // (ASR, LSL, LSR, ROR, RRX)=MOVsi, MVN
236 "(t2|t)RORri", "(t2)?RRX", "t2MOV", "tROR")>;
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| D | ARMScheduleSwift.td | 155 // ASR,LSL,ROR,RRX
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| D | ARMScheduleR52.td | 339 (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX")>;
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| D | ARMExpandPseudoInsts.cpp | 1382 case ARM::RRX: { in ExpandMI()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSubtargetInfo.inc | 5471 { 1, 1, 2, 916, 918 }, // 720 RRX
6476 { 1, 13, 15, 3368, 3370 }, // 720 RRX
7481 { 1, 265, 266, 6294, 6296 }, // 720 RRX
11261 {DBGFIELD("RRX") 1, false, false, 1, 1, 1, 1, 0, 0}, // #720
12668 {DBGFIELD("RRX") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #720
14075 {DBGFIELD("RRX") 1, false, false, 3, 1, 3, 1, 0, 1}, // #720
15482 {DBGFIELD("RRX") 1, false, false, 4, 1, 1, 1, 0, 0}, // #720
19390 case 720: // RRX
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