Home
last modified time | relevance | path

Searched refs:Reg1 (Results 1 – 25 of 92) sorted by relevance

1234

/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp447 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
464 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
467 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
470 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
473 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
476 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
479 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
483 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
490 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
493 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp504 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
521 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
524 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
527 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
530 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
533 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
536 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
540 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
547 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
550 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DLocked.cpp86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
89 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
95 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
98 GPRRegister::Encoded_Reg_##Reg1); \ in TEST_F()
101 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
107 ASSERT_EQ(V0, test.Reg1()) << TestString; \ in TEST_F()
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
114 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
120 GPRRegister::Encoded_Reg_##Reg1 < 4) { \ in TEST_F()
[all …]
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DLocked.cpp89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
92 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
97 __ mov(IceType_i##Size, Encoded_GPR_##Reg1(), Immediate(Value1)); \ in TEST_F()
98 __ xchg(IceType_i##Size, Encoded_GPR_##Reg0(), Encoded_GPR_##Reg1()); \ in TEST_F()
100 __ And(IceType_i32, Encoded_GPR_##Reg1(), Immediate(Mask##Size)); \ in TEST_F()
105 ASSERT_EQ(V0, test.Reg1()) << TestString; \ in TEST_F()
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
112 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
117 TestImplSize(Reg0, Reg1, 8); \ in TEST_F()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp874 RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {} in RegPairInfo()
875 unsigned Reg1; member
905 RPI.Reg1 = CSI[i].getReg(); in computeCalleeSaveRegisterPairs()
907 assert(AArch64::GPR64RegClass.contains(RPI.Reg1) || in computeCalleeSaveRegisterPairs()
908 AArch64::FPR64RegClass.contains(RPI.Reg1)); in computeCalleeSaveRegisterPairs()
909 RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1); in computeCalleeSaveRegisterPairs()
934 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || in computeCalleeSaveRegisterPairs()
935 RPI.Reg1 + 1 == RPI.Reg2))) && in computeCalleeSaveRegisterPairs()
974 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
992 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1); in spillCalleeSavedRegisters()
[all …]
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
614 uint16_t Reg1; variable
616 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} in MCRegUnitRootIterator()
620 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
636 Reg0 = Reg1;
637 Reg1 = 0;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp1142 unsigned Reg1 = AArch64::NoRegister; member
1178 RPI.Reg1 = CSI[i].getReg(); in computeCalleeSaveRegisterPairs()
1180 assert(AArch64::GPR64RegClass.contains(RPI.Reg1) || in computeCalleeSaveRegisterPairs()
1181 AArch64::FPR64RegClass.contains(RPI.Reg1)); in computeCalleeSaveRegisterPairs()
1182 RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1); in computeCalleeSaveRegisterPairs()
1194 if ((RPI.Reg1 == AArch64::LR || RPI.Reg2 == AArch64::LR) && in computeCalleeSaveRegisterPairs()
1216 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || in computeCalleeSaveRegisterPairs()
1217 RPI.Reg1 + 1 == RPI.Reg2))) && in computeCalleeSaveRegisterPairs()
1272 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
1290 LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI); in spillCalleeSavedRegisters()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp408 bool parseAddress(bool &HaveReg1, Register &Reg1,
772 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
790 if (parseRegister(Reg1)) in parseAddress()
837 Register Reg1, Reg2; in parseAddress() local
841 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) in parseAddress()
848 if (parseAddressRegister(Reg1)) in parseAddress()
850 Base = Regs[Reg1.Num]; in parseAddress()
865 if (parseAddressRegister(Reg1)) in parseAddress()
870 Index = Regs[Reg1.Num]; in parseAddress()
872 Base = Regs[Reg1.Num]; in parseAddress()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCRegisterInfo.h79 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
80 return contains(Reg1) && contains(Reg2); in contains()
643 uint16_t Reg1 = 0; variable
651 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
667 Reg0 = Reg1;
668 Reg1 = 0;
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.h73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
DMipsAsmPrinter.cpp769 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
778 unsigned Temp = Reg1; in EmitInstrRegReg()
779 Reg1 = Reg2; in EmitInstrRegReg()
783 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
789 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
793 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
800 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
804 unsigned temp = Reg1; in EmitMovFPIntPair()
805 Reg1 = Reg2; in EmitMovFPIntPair()
808 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
DMipsTargetStreamer.h111 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
113 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
115 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
117 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
DMips16InstrInfo.cpp263 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
272 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
276 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
277 MIB3.addReg(Reg1); in adjustStackPtrBig()
281 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTargetInstrInfoImpl.cpp78 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() local
84 if (HasDef && Reg0 == Reg1 && in commuteInstruction()
91 Reg0 = Reg1; in commuteInstruction()
102 .addReg(Reg1, getKillRegState(Reg2IsKill)); in commuteInstruction()
106 .addReg(Reg1, getKillRegState(Reg2IsKill)); in commuteInstruction()
111 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsAsmPrinter.h95 unsigned Reg1, unsigned Reg2);
98 unsigned Reg1, unsigned Reg2, unsigned Reg3);
101 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
DMipsTargetStreamer.h127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
133 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
135 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
DMipsAsmPrinter.cpp824 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
833 unsigned Temp = Reg1; in EmitInstrRegReg()
834 Reg1 = Reg2; in EmitInstrRegReg()
838 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
844 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
848 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
855 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
859 unsigned temp = Reg1; in EmitMovFPIntPair()
860 Reg1 = Reg2; in EmitMovFPIntPair()
863 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
DMips16InstrInfo.cpp283 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
292 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
296 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
297 MIB3.addReg(Reg1); in adjustStackPtrBig()
301 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
DMicroMipsSizeReduction.cpp372 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
381 if (Registers[i] == Reg1) { in ConsecutiveRegisters()
400 unsigned Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
403 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
472 unsigned Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
475 if (Reg1 != Reg2) in ReduceXWtoXWP()
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrBuilder.h84 unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) { in addRegReg() argument
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0) in addRegReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp170 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
172 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
185 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
191 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
197 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
200 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
203 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
206 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
210 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII() argument
216 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRIII()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrBuilder.h116 unsigned Reg1, bool isKill1, in addRegReg() argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCRegisterInfo.h85 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
86 return contains(Reg1) && contains(Reg2); in contains()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
155 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
174 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
183 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
189 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h144 unsigned Reg1, bool isKill1, in addRegReg() argument
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()

1234