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Searched refs:RegList1 (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenCallingConv.inc96 static const MCPhysReg RegList1[] = {
99 if (unsigned Reg = State.AllocateReg(RegList1)) {
152 static const MCPhysReg RegList1[] = {
158 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
212 static const MCPhysReg RegList1[] = {
215 if (unsigned Reg = State.AllocateReg(RegList1)) {
246 static const MCPhysReg RegList1[] = {
252 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
299 static const MCPhysReg RegList1[] = {
302 if (unsigned Reg = State.AllocateReg(RegList1)) {
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenCallingConv.inc143 static const unsigned RegList1[] = {
146 if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
175 static const unsigned RegList1[] = {
178 if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
315 static const unsigned RegList1[] = {
318 if (unsigned Reg = State.AllocateReg(RegList1, 2)) {
375 static const unsigned RegList1[] = {
378 if (unsigned Reg = State.AllocateReg(RegList1, 2)) {
407 static const unsigned RegList1[] = {
410 if (unsigned Reg = State.AllocateReg(RegList1, 4)) {
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc134 static const MCPhysReg RegList1[] = {
140 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
274 static const MCPhysReg RegList1[] = {
277 if (unsigned Reg = State.AllocateReg(RegList1)) {
379 static const MCPhysReg RegList1[] = {
382 if (unsigned Reg = State.AllocateReg(RegList1)) {
433 static const MCPhysReg RegList1[] = {
436 if (unsigned Reg = State.AllocateReg(RegList1)) {
510 static const MCPhysReg RegList1[] = {
513 if (unsigned Reg = State.AllocateReg(RegList1)) {
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc176 static const MCPhysReg RegList1[] = {
179 if (unsigned Reg = State.AllocateReg(RegList1)) {
398 static const MCPhysReg RegList1[] = {
401 if (unsigned Reg = State.AllocateReg(RegList1)) {
430 static const MCPhysReg RegList1[] = {
433 if (unsigned Reg = State.AllocateReg(RegList1)) {
582 static const MCPhysReg RegList1[] = {
585 if (unsigned Reg = State.AllocateReg(RegList1)) {
642 static const MCPhysReg RegList1[] = {
645 if (unsigned Reg = State.AllocateReg(RegList1)) {
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc136 static const MCPhysReg RegList1[] = {
142 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
380 static const MCPhysReg RegList1[] = {
386 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
665 static const MCPhysReg RegList1[] = {
668 if (unsigned Reg = State.AllocateReg(RegList1)) {
856 static const MCPhysReg RegList1[] = {
862 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
965 static const MCPhysReg RegList1[] = {
971 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp299 static const MCPhysReg RegList1[] = { in CC_Hexagon64() local
305 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { in CC_Hexagon64()