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Searched refs:RegList2 (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenCallingConv.inc155 static const MCPhysReg RegList2[] = {
158 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
222 static const MCPhysReg RegList2[] = {
225 if (unsigned Reg = State.AllocateReg(RegList2)) {
249 static const MCPhysReg RegList2[] = {
252 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
310 static const MCPhysReg RegList2[] = {
313 if (unsigned Reg = State.AllocateReg(RegList2)) {
406 static const MCPhysReg RegList2[] = {
409 if (unsigned Reg = State.AllocateReg(RegList2)) {
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc137 static const MCPhysReg RegList2[] = {
140 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
284 static const MCPhysReg RegList2[] = {
287 if (unsigned Reg = State.AllocateReg(RegList2)) {
443 static const MCPhysReg RegList2[] = {
446 if (unsigned Reg = State.AllocateReg(RegList2)) {
520 static const MCPhysReg RegList2[] = {
523 if (unsigned Reg = State.AllocateReg(RegList2)) {
660 static const MCPhysReg RegList2[] = {
666 if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) {
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenCallingConv.inc189 static const unsigned RegList2[] = {
192 if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
328 static const unsigned RegList2[] = {
331 if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
515 static const unsigned RegList2[] = {
518 if (unsigned Reg = State.AllocateReg(RegList2, 6)) {
652 static const unsigned RegList2[] = {
655 if (unsigned Reg = State.AllocateReg(RegList2, 6)) {
707 static const unsigned RegList2[] = {
710 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 4)) {
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc188 static const MCPhysReg RegList2[] = {
191 if (unsigned Reg = State.AllocateReg(RegList2)) {
444 static const MCPhysReg RegList2[] = {
447 if (unsigned Reg = State.AllocateReg(RegList2)) {
595 static const MCPhysReg RegList2[] = {
598 if (unsigned Reg = State.AllocateReg(RegList2)) {
654 static const MCPhysReg RegList2[] = {
657 if (unsigned Reg = State.AllocateReg(RegList2)) {
884 static const MCPhysReg RegList2[] = {
887 if (unsigned Reg = State.AllocateReg(RegList2)) {
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc139 static const MCPhysReg RegList2[] = {
142 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
383 static const MCPhysReg RegList2[] = {
386 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
675 static const MCPhysReg RegList2[] = {
678 if (unsigned Reg = State.AllocateReg(RegList2)) {
859 static const MCPhysReg RegList2[] = {
862 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
968 static const MCPhysReg RegList2[] = {
971 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp302 static const MCPhysReg RegList2[] = { in CC_Hexagon64() local
305 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { in CC_Hexagon64()