/external/llvm/lib/CodeGen/GlobalISel/ |
D | RegisterBank.cpp | 20 const unsigned RegisterBank::InvalidID = UINT_MAX; 22 RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Size(0) {} in RegisterBank() function in RegisterBank 24 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify() 55 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers() 60 bool RegisterBank::isValid() const { in isValid() 66 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in operator ==() 75 void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump() 79 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, in print()
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D | RegisterBankInfo.cpp | 43 RegBanks.reset(new RegisterBank[NumRegBanks]); in RegisterBankInfo() 48 const RegisterBank &RegBank = getRegBank(Idx); in verify() 60 RegisterBank &RegBank = getRegBank(ID); in createRegisterBank() 61 assert(RegBank.getID() == RegisterBank::InvalidID && in createRegisterBank() 70 RegisterBank &RB = getRegBank(ID); in addRegBankCoverage() 168 const RegisterBank * 176 if (RegClassOrBank.is<const RegisterBank *>()) in getRegBank() 177 return RegClassOrBank.get<const RegisterBank *>(); in getRegBank() 185 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints() 195 const RegisterBank &RegBank = getRegBankFromRegClass(*RC); in getRegBankFromConstraints() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
D | RegisterBank.cpp | 21 const unsigned RegisterBank::InvalidID = UINT_MAX; 23 RegisterBank::RegisterBank( in RegisterBank() function in RegisterBank 31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify() 60 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers() 65 bool RegisterBank::isValid() const { in isValid() 71 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in operator ==() 81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump() 86 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, in print()
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D | RegisterBankInfo.cpp | 59 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks, in RegisterBankInfo() 73 const RegisterBank &RegBank = getRegBank(Idx); in verify() 83 const RegisterBank * 91 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank() 111 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints() 121 const RegisterBank &RegBank = getRegBankFromRegClass(*RC); in getRegBankFromConstraints() 136 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister() 192 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl() 196 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr; in getInstrMappingImpl() 234 const RegisterBank *RegBank) { in hashPartialMapping() [all …]
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/external/llvm/include/llvm/CodeGen/GlobalISel/ |
D | RegisterBankInfo.h | 54 const RegisterBank *RegBank; 60 const RegisterBank &RegBank) in PartialMapping() 169 const RegisterBank &RegBank); 290 std::unique_ptr<RegisterBank[]> RegBanks; 295 std::unique_ptr<const RegisterBank *[]> VTToRegBank; 350 RegisterBank &getRegBank(unsigned ID) { in getRegBank() 356 const RegisterBank *getRegBankForType(MVT::SimpleValueType SVT) const { in getRegBankForType() 370 void recordRegBankForType(const RegisterBank &RegBank, 374 new const RegisterBank *[MVT::SimpleValueType::LAST_VALUETYPE]); 410 const RegisterBank * [all …]
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D | RegisterBank.h | 29 class RegisterBank { 44 RegisterBank(); 77 bool operator==(const RegisterBank &OtherRB) const; 78 bool operator!=(const RegisterBank &OtherRB) const { 95 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
D | RegisterBankInfo.h | 32 class RegisterBank; variable 59 const RegisterBank *RegBank; 65 const RegisterBank &RegBank) in PartialMapping() 385 RegisterBank **RegBanks; 416 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks); 429 RegisterBank &getRegBank(unsigned ID) { in getRegBank() 461 const RegisterBank &RegBank) const; 469 const RegisterBank &RegBank) const; 542 const RegisterBank * 573 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() [all …]
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D | RegisterBank.h | 29 class RegisterBank { 44 RegisterBank(unsigned ID, const char *Name, unsigned Size, 75 bool operator==(const RegisterBank &OtherRB) const; 76 bool operator!=(const RegisterBank &OtherRB) const { 93 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
D | RegisterBankEmitter.cpp | 29 class RegisterBank { class 44 RegisterBank(const Record &TheDef) in RegisterBank() function in __anon6b49e9f90111::RegisterBank 112 const std::vector<RegisterBank> &Banks); 114 const std::vector<RegisterBank> &Banks); 116 std::vector<RegisterBank> &Banks); 131 const std::vector<RegisterBank> &Banks) { in emitHeader() 147 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() 215 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() 284 std::vector<RegisterBank> Banks; in run() 287 RegisterBank Bank(*V); in run()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64RegisterBankInfo.cpp | 35 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() 46 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo() 58 const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID); in AArch64RegisterBankInfo() 67 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost() 68 const RegisterBank &B, in copyCost() 79 const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass( in getRegBankFromRegClass()
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D | AArch64RegisterBankInfo.h | 45 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 60 const RegisterBank &
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64RegisterBankInfo.h | 64 unsigned ValLength, const RegisterBank &RB); 120 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 123 const RegisterBank &
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D | AArch64RegisterBanks.td | 14 def GPRRegBank : RegisterBank<"GPR", [GPR64all]>; 17 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>; 20 def CCRegBank : RegisterBank<"CC", [CCR]>;
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D | AArch64RegisterBankInfo.cpp | 52 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() 57 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo() 62 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo() 205 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost() 206 const RegisterBank &B, in copyCost() 226 const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass( in getRegBankFromRegClass() 498 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping() 499 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping() 523 const RegisterBank &DstRB = in getInstrMapping() 525 const RegisterBank &SrcRB = in getInstrMapping()
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D | AArch64InstructionSelector.cpp | 142 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank() 186 const RegisterBank *PrevOpBank = nullptr; in unsupportedBinOp() 203 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp() 352 const RegisterBank &RegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy() 362 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy() 394 const RegisterBank *RB = nullptr; in selectCopy() 396 RB = RegClassOrBank.get<const RegisterBank *>(); in selectCopy() 605 const RegisterBank &RB = *RBI.getRegBank(LHS, MRI, TRI); in selectCompareBranch() 736 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in select() 810 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select() [all …]
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenRegisterBank.inc | 26 static RegisterBank *RegBanks[]; 111 RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* Size */ 32, /* CoveredReg… 112 RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* Covere… 113 RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* Covered… 116 RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPURegisterBanks.td | 10 def SGPRRegBank : RegisterBank<"SGPR", 14 def VGPRRegBank : RegisterBank<"VGPR", 18 def SCCRegBank : RegisterBank <"SCC", [SCC_CLASS ]>;
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D | AMDGPURegisterBankInfo.h | 55 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 58 const RegisterBank &
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenRegisterBank.inc | 25 static RegisterBank *RegBanks[]; 80 RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRe… 81 RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredReg… 84 RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
D | X86GenRegisterBank.inc | 25 static RegisterBank *RegBanks[]; 108 RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegC… 109 RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* Covered… 112 RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
D | MipsGenRegisterBank.inc | 24 static RegisterBank *RegBanks[]; 61 RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* Covered… 64 RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/MIRParser/ |
D | MIParser.h | 26 class RegisterBank; variable 40 const RegisterBank *RegBank; 47 using Name2RegBankMap = StringMap<const RegisterBank *>;
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/GlobalISel/ |
D | RegisterBank.td | 1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===// 13 class RegisterBank<string name, list<RegisterClass> classes> {
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMRegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>; 14 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86RegisterBanks.td | 14 def GPRRegBank : RegisterBank<"GPR", [GR64]>; 17 def VECRRegBank : RegisterBank<"VECR", [VR512]>;
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