| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 60 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses(); in runEnums() local
61 if (!RegisterClasses.empty()) { in runEnums()
66 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { in runEnums()
68 OS << " " << RegisterClasses[i]->getName() << "RegClassID"; in runEnums()
333 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); in runMCDesc() local
339 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { in runMCDesc()
340 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc()
372 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { in runMCDesc()
373 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc()
394 << RegisterClasses.size() << ");\n\n"; in runMCDesc()
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| D | AsmWriterEmitter.cpp | 706 ArrayRef<CodeGenRegisterClass*> RegisterClasses = in EmitRegIsInRegClass() local
713 for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) { in EmitRegIsInRegClass()
715 O << " RC_" << RegisterClasses[I]->getName(); in EmitRegIsInRegClass()
731 for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) { in EmitRegIsInRegClass()
732 const CodeGenRegisterClass &RC = *RegisterClasses[I]; in EmitRegIsInRegClass()
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| D | AsmMatcherEmitter.cpp | 573 std::map<Record*, ClassInfo*> RegisterClasses; member in __anonb4a425710111::AsmMatcherInfo
1021 RegisterClasses[it->first] = RegisterSetClasses[it->second]; in BuildRegisterClasses()
1027 ClassInfo *CI = RegisterClasses[Rec]; in BuildRegisterClasses()
1264 Op.Class = RegisterClasses[RegRecord]; in BuildInfo()
1678 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end(); in EmitValidateOperandClass()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 122 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums() local
123 if (!RegisterClasses.empty()) { in runEnums()
126 assert(RegisterClasses.size() <= 0xffff && in runEnums()
133 for (const auto &RC : RegisterClasses) in runEnums()
981 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc() local
989 for (const auto &RC : RegisterClasses) { in runMCDesc()
1029 for (const auto &RC : RegisterClasses) { in runMCDesc()
1074 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " in runMCDesc()
1138 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader() local
1140 if (!RegisterClasses.empty()) { in runTargetHeader()
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| D | AsmMatcherEmitter.cpp | 715 RegisterClassesTy RegisterClasses; member in __anon4cf19d450111::AsmMatcherInfo
1305 RegisterClasses[it->first] = RegisterSetClasses[it->second]; in buildRegisterClasses()
1309 ClassInfo *CI = RegisterClasses[Rec]; in buildRegisterClasses()
1545 Op.Class = RegisterClasses[RegRecord]; in buildInfo()
2237 for (const auto &RC : Info.RegisterClasses) in emitValidateOperandClass()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 136 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums() local
137 if (!RegisterClasses.empty()) { in runEnums()
140 assert(RegisterClasses.size() <= 0xffff && in runEnums()
147 for (const auto &RC : RegisterClasses) in runEnums()
990 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc() local
998 for (const auto &RC : RegisterClasses) { in runMCDesc()
1036 for (const auto &RC : RegisterClasses) { in runMCDesc()
1078 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " in runMCDesc()
1143 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader() local
1145 if (!RegisterClasses.empty()) { in runTargetHeader()
[all …]
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| D | AsmMatcherEmitter.cpp | 731 RegisterClassesTy RegisterClasses; member in __anon267ecc9d0111::AsmMatcherInfo
1327 RegisterClasses[it->first] = RegisterSetClasses[it->second]; in buildRegisterClasses()
1331 ClassInfo *CI = RegisterClasses[Rec]; in buildRegisterClasses()
1578 Op.Class = RegisterClasses[RegRecord]; in buildInfo()
2491 for (const auto &RC : Info.RegisterClasses) in emitValidateOperandClass()
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| D | CodeGenSchedule.cpp | 1527 RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses"); in collectRegisterFiles() local
1529 for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) { in collectRegisterFiles()
1531 CGRF.Costs.emplace_back(RegisterClasses[I], Cost); in collectRegisterFiles()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/GlobalISel/ |
| D | RegisterBank.td | 15 list<RegisterClass> RegisterClasses = classes;
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| D | RegisterFile.h | 112 addRegisterFile(llvm::ArrayRef<llvm::MCRegisterCostEntry> RegisterClasses,
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| D | RegisterAliasing.h | 102 RegisterClasses; member
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| D | RegisterAliasing.cpp | 76 auto &Found = RegisterClasses[RegClassIndex]; in getRegisterClass()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 5557 const TargetRegisterClass* const RegisterClasses[] = {
7305 : TargetRegisterInfo(MipsRegInfoDesc, RegisterClasses, RegisterClasses+73,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 6177 const TargetRegisterClass* const RegisterClasses[] = {
7758 : TargetRegisterInfo(X86RegInfoDesc, RegisterClasses, RegisterClasses+86,
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 3463 const TargetRegisterClass* const RegisterClasses[] = {
5025 : TargetRegisterInfo(X86RegInfoDesc, RegisterClasses, RegisterClasses+40,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 6921 const TargetRegisterClass* const RegisterClasses[] = {
13678 : TargetRegisterInfo(ARMRegInfoDesc, RegisterClasses, RegisterClasses+103,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 7907 const TargetRegisterClass* const RegisterClasses[] = {
19280 : TargetRegisterInfo(AArch64RegInfoDesc, RegisterClasses, RegisterClasses+100,
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