| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | atomicrmx.ll | 14 ;CHK32: SC_R6
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| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | atomicrmx.ll | 14 ;CHK32: SC_R6
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 99 SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in expandAtomicCmpSwapSubword()
227 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in expandAtomicCmpSwap()
323 SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in expandAtomicBinOpSubword()
504 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in expandAtomicBinOp()
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| D | MipsSERegisterInfo.cpp | 100 case Mips::SC_R6: in getLoadStoreOffsetSizeInBits()
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| D | Mips32r6InstrInfo.td | 948 def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 241 case Mips::SC_R6: in isBasePlusOffsetMemoryAccess()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 250 case Mips::SC_R6: in isBasePlusOffsetMemoryAccess()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 568 SC_R6 = ((4U << 3) + 6), enumerator
1736 case SC_R6: { in InstructionType()
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| D | disasm-mips.cc | 1685 case SC_R6: { in DecodeTypeImmediateSPECIAL3()
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| D | assembler-mips.cc | 2316 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, SC_R6); in sc()
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| D | simulator-mips.cc | 6816 case SC_R6: { in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 587 SC_R6 = ((4U << 3) + 6), enumerator
1802 case SC_R6: in InstructionType()
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| D | disasm-mips64.cc | 1987 case SC_R6: { in DecodeTypeImmediateSPECIAL3()
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| D | assembler-mips64.cc | 2479 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, SC_R6); in sc()
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| D | simulator-mips64.cc | 7155 case SC_R6: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1125 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in emitAtomicBinary()
1270 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in emitAtomicBinaryPartword()
1413 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in emitAtomicCmpSwap()
1525 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in emitAtomicCmpSwapPartword()
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| D | Mips32r6InstrInfo.td | 834 def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1814 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ in DecodeSpecial3LlSc()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1387 1754799U, // SC_R6
3101 0U, // SC_R6
4631 // SC, SCD, SCD_R6, SC_MM, SC_R6
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| D | MipsGenDisassemblerTables.inc | 4015 /* 1606 */ MCD_OPC_Decode, 218, 10, 223, 1, // Opcode: SC_R6
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 2043 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ in DecodeSpecial3LlSc()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 3438 4491353U, // SC_R6
6069 0U, // SC_R6
6664 // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6
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| D | MipsGenMCCodeEmitter.inc | 2223 UINT64_C(2080374822), // SC_R6
6449 case Mips::SC_R6: {
9949 …_HasStdEnc | Feature_IsPTR32bit | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // SC_R6 = 2210
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| D | MipsGenInstrInfo.inc | 2225 SC_R6 = 2210,
6270 …odeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2210 = SC_R6
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| D | MipsGenDisassemblerTables.inc | 6599 /* 2042 */ MCD::OPC_Decode, 162, 17, 228, 2, // Opcode: SC_R6
|