| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 160 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; in getFCmpCondCode()
168 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; in getFCmpCondCode()
187 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
198 return ISD::SETNE; in getICmpCondCode()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 20 IntRegs:$fval, SETNE)),
80 // and similarly for SETNE
83 IntRegs:$fval, SETNE)),
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 527 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
528 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
537 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
538 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
1938 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1943 Cond = ISD::SETNE; in SimplifySetCC()
1972 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1981 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
2087 case ISD::SETNE: return DAG.getConstant(1, VT); in SimplifySetCC()
2104 case ISD::SETNE: in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 465 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
627 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
664 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); in PromoteIntRes_XMULO()
669 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); in PromoteIntRes_XMULO()
816 case ISD::SETNE: in PromoteSetCCOperands()
1703 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
1733 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
2009 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2012 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandIntRes_SADDSUBO()
2260 RHS, DAG.getConstant(0, VT), ISD::SETNE); in ExpandIntRes_XMULO()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 167 case ISD::SETNE: in softenSetCCOperands()
1293 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in simplifySetCCWithAnd()
1382 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1387 Cond = ISD::SETNE; in SimplifySetCC()
1416 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1425 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1493 (!N1C->isNullValue() && Cond == ISD::SETNE); in SimplifySetCC()
1582 case ISD::SETNE: return DAG.getConstant(1, dl, VT); in SimplifySetCC()
1599 case ISD::SETNE: in SimplifySetCC()
1622 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 559 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
751 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
793 ISD::SETNE); in PromoteIntRes_XMULO()
798 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); in PromoteIntRes_XMULO()
950 case ISD::SETNE: { in PromoteSetCCOperands()
1967 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
1998 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
2285 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2288 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandIntRes_SADDSUBO()
2562 ISD::SETNE); in ExpandIntRes_XMULO()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 453 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
494 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
555 case ISD::SETNE: return PPC::PRED_NE; in getPredicateForSetCC()
595 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE in getCRIdxForSetCC()
629 case ISD::SETNE: { in SelectSETCC()
662 case ISD::SETNE: { in SelectSETCC()
1014 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && in Select()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 172 case ISD::SETNE: in softenSetCCOperands()
1807 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in simplifySetCCWithAnd()
1896 NewCond = ISD::CondCode::SETNE; in optimizeSetCCOfSignedTruncationCheck()
1900 NewCond = ISD::CondCode::SETNE; in optimizeSetCCOfSignedTruncationCheck()
1974 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1979 Cond = ISD::SETNE; in SimplifySetCC()
2008 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
2017 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
2066 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); in SimplifySetCC()
2089 (!N1C->isNullValue() && Cond == ISD::SETNE); in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 558 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
758 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
829 ISD::SETNE); in PromoteIntRes_XMULO()
834 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); in PromoteIntRes_XMULO()
990 case ISD::SETNE: { in PromoteSetCCOperands()
2140 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
2171 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
2471 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2474 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandIntRes_SADDSUBO()
2723 ISD::SETNE); in ExpandIntRes_XMULO()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 501 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
502 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
503 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
504 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
521 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
522 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
523 CCs[RTLIB::UO_F128] = ISD::SETNE; in InitCmpLibcallCCs()
524 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
|
| D | Analysis.cpp | 186 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
201 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
|
| /external/mesa3d/src/mesa/x86/ |
| D | common_x86_asm.S | 66 SETNE (AL)
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 767 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
768 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
769 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
770 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
787 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
788 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
789 CCs[RTLIB::UO_F128] = ISD::SETNE; in InitCmpLibcallCCs()
790 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
|
| D | Analysis.cpp | 187 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
202 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 737 SETNE, // 1 X 1 1 0 True if not equal enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 875 SETNE, // 1 X 1 1 0 True if not equal enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); in ARMTargetLowering()
210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); in ARMTargetLowering()
211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); in ARMTargetLowering()
212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); in ARMTargetLowering()
213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); in ARMTargetLowering()
214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); in ARMTargetLowering()
215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); in ARMTargetLowering()
228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); in ARMTargetLowering()
229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); in ARMTargetLowering()
230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); in ARMTargetLowering()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 938 SETNE, // 1 X 1 1 0 True if not equal enumerator
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 91 [{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
133 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
156 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 44 defm NE : ComparisonInt<SETNE, "ne ">;
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 93 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 44 defm NE : ComparisonInt<SETNE, "ne ", 0x47, 0x52>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 263 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE }, in ARMTargetLowering()
264 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE }, in ARMTargetLowering()
265 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE }, in ARMTargetLowering()
266 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE }, in ARMTargetLowering()
267 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE }, in ARMTargetLowering()
268 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE }, in ARMTargetLowering()
269 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE }, in ARMTargetLowering()
273 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE }, in ARMTargetLowering()
274 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE }, in ARMTargetLowering()
275 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE }, in ARMTargetLowering()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenDAGISel.inc | 1417 /* 2541*/ OPC_CheckCondCode, ISD::SETNE,
1430 …i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (b…
1463 /* 2619*/ OPC_CheckCondCode, ISD::SETNE,
1476 …i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (b…
1514 /* 2702*/ OPC_CheckCondCode, ISD::SETNE,
1527 …P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (b…
1561 /* 2781*/ OPC_CheckCondCode, ISD::SETNE,
1574 …P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (b…
1636 /* 2903*/ OPC_CheckCondCode, ISD::SETNE,
1650 …:$lhs, (imm:{ *:[i64] })<<P:Predicate_PowerOf2LO>>:$mask), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (b…
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 192 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE }, in ARMTargetLowering()
193 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE }, in ARMTargetLowering()
194 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE }, in ARMTargetLowering()
195 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE }, in ARMTargetLowering()
196 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE }, in ARMTargetLowering()
197 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE }, in ARMTargetLowering()
198 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE }, in ARMTargetLowering()
202 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE }, in ARMTargetLowering()
203 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE }, in ARMTargetLowering()
204 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE }, in ARMTargetLowering()
[all …]
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