| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.h | 312 SFENCE, enumerator
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| D | X86InstrInfo.td | 115 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
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| D | X86GenInstrInfo.inc | 2379 SFENCE = 2363,
6547 …0, 0, "SFENCE", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x15c000…
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| D | X86InstrSSE.td | 3192 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3199 def : Pat<(X86SFence), (SFENCE)>;
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| D | X86GenAsmWriter.inc | 2376 8286U, // SFENCE
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| D | X86GenAsmWriter1.inc | 2376 6208U, // SFENCE
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| D | X86GenAsmMatcher.inc | 4891 { X86::SFENCE, "sfence", Convert, { }, 0},
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| D | X86GenDisassemblerTables.inc | 28375 "SFENCE"
133235 0x93b, /* SFENCE*/
136562 0x93b, /* SFENCE*/
139913 0x93b, /* SFENCE*/
143269 0x93b, /* SFENCE*/
146620 0x93b, /* SFENCE*/
149981 0x93b, /* SFENCE*/
153328 0x93b, /* SFENCE*/
156680 0x93b, /* SFENCE*/
160027 0x93b, /* SFENCE*/
[all …]
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| D | X86ISelLowering.cpp | 10194 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); in LowerMEMBARRIER()
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| D | X86GenDAGISel.inc | 26257 /*53915*/ OPC_MorphNodeTo, TARGET_VAL(X86::SFENCE), 0|OPFL_Chain,
26260 // Dst: (SFENCE)
46350 /*SwitchOpcode*/ 8, TARGET_VAL(X86ISD::SFENCE),// ->96812
46353 /*96806*/ OPC_MorphNodeTo, TARGET_VAL(X86::SFENCE), 0|OPFL_Chain,
46356 // Dst: (SFENCE)
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86SchedSkylakeClient.td | 698 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
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| D | X86SchedBroadwell.td | 698 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
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| D | X86SchedHaswell.td | 1053 def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
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| D | X86SchedSkylakeServer.td | 722 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
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| D | X86InstrSSE.td | 3125 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 5517 {DBGFIELD("SFENCE") 1, false, false, 6, 2, 1, 1, 0, 0}, // #805
6733 {DBGFIELD("SFENCE") 2, false, false, 90, 3, 20, 1, 0, 0}, // #805
7949 {DBGFIELD("SFENCE") 1, false, false, 603, 2, 1, 1, 0, 0}, // #805
9165 {DBGFIELD("SFENCE") 2, false, false, 90, 3, 20, 1, 0, 0}, // #805
10381 {DBGFIELD("SFENCE") 1, false, false, 2955, 3, 1, 1, 0, 0}, // #805
11597 {DBGFIELD("SFENCE") 2, false, false, 90, 3, 20, 1, 0, 0}, // #805
12813 {DBGFIELD("SFENCE") 1, false, false, 1583, 1, 1, 1, 0, 0}, // #805
14029 {DBGFIELD("SFENCE") 2, false, false, 90, 3, 20, 1, 0, 0}, // #805
15245 {DBGFIELD("SFENCE") 1, false, false, 6, 1, 1, 1, 0, 0}, // #805
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| D | X86GenGlobalISel.inc | 9905 // (intrinsic_void 6398:{ *:[iPTR] }) => (SFENCE)
9906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SFENCE,
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| D | X86GenAsmWriter.inc | 4511 16840U, // SFENCE
20017 0U, // SFENCE
35523 0U, // SFENCE
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| D | X86GenAsmWriter1.inc | 4191 13620U, // SFENCE
19697 0U, // SFENCE
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| D | X86GenInstrInfo.inc | 2758 SFENCE = 2743,
16337 SFENCE = 805,
20557 …ledSideEffects), 0x2b80002078ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2743 = SFENCE
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| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 1701 #define SFENCE sfence macro
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| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter.inc | 2612 14305U, // SFENCE
8883 0U, // SFENCE
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| D | X86GenAsmWriter1.inc | 2612 11421U, // SFENCE
8883 0U, // SFENCE
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| D | X86GenDisassemblerTables.inc | 17676 /* SFENCE */
51576 0xa23, /* SFENCE */
53022 0xa23, /* SFENCE */
53264 0xa23, /* SFENCE */
53349 0xa23, /* SFENCE */
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 3682 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
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