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Searched refs:SOC_REGS_PHY_BASE (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/arch/arm/mach-mvebu/include/mach/
Dsoc.h47 #define SOC_REGS_PHY_BASE 0xd0000000 macro
49 #define SOC_REGS_PHY_BASE 0xf0000000 macro
51 #define SOC_REGS_PHY_BASE 0xf1000000 macro
53 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
/external/u-boot/arch/arm/mach-mvebu/
Dcpu.c396 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); in arch_cpu_init()
397 set_cbar(SOC_REGS_PHY_BASE + 0xC000); in arch_cpu_init()
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr_ml_wrapper.h17 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
Dmv_ddr_plat.h16 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_axp.h78 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
/external/u-boot/drivers/pci/
Dpci_mvebu.c426 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); in pci_init_board()