Searched refs:SOC_REGS_PHY_BASE (Results 1 – 6 of 6) sorted by relevance
47 #define SOC_REGS_PHY_BASE 0xd0000000 macro49 #define SOC_REGS_PHY_BASE 0xf0000000 macro51 #define SOC_REGS_PHY_BASE 0xf1000000 macro53 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
396 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); in arch_cpu_init()397 set_cbar(SOC_REGS_PHY_BASE + 0xC000); in arch_cpu_init()
17 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
16 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
78 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
426 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); in pci_init_board()