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Searched refs:SPRN_L1CFG0 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/powerpc/include/asm/
Dprocessor.h482 #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ macro
736 #define L1CFG0 SPRN_L1CFG0
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dfdt.c388 u32 l1cfg0 = mfspr(SPRN_L1CFG0); in ft_fixup_cache()
Dstart.S1807 mfspr r3,SPRN_L1CFG0