1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 */
8
9 #include <common.h>
10 #include <environment.h>
11 #include <linux/libfdt.h>
12 #include <fdt_support.h>
13 #include <asm/processor.h>
14 #include <linux/ctype.h>
15 #include <asm/io.h>
16 #include <asm/fsl_fdt.h>
17 #include <asm/fsl_portals.h>
18 #include <fsl_qbman.h>
19 #include <hwconfig.h>
20 #ifdef CONFIG_FSL_ESDHC
21 #include <fsl_esdhc.h>
22 #endif
23 #ifdef CONFIG_SYS_DPAA_FMAN
24 #include <fsl_fman.h>
25 #endif
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 extern void ft_qe_setup(void *blob);
30 extern void ft_fixup_num_cores(void *blob);
31 extern void ft_srio_setup(void *blob);
32
33 #ifdef CONFIG_MP
34 #include "mp.h"
35
ft_fixup_cpu(void * blob,u64 memory_limit)36 void ft_fixup_cpu(void *blob, u64 memory_limit)
37 {
38 int off;
39 phys_addr_t spin_tbl_addr = get_spin_phys_addr();
40 u32 bootpg = determine_mp_bootpg(NULL);
41 u32 id = get_my_id();
42 const char *enable_method;
43 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
44 int ret;
45 int tdm_hwconfig_enabled = 0;
46 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
47 #endif
48
49 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
50 while (off != -FDT_ERR_NOTFOUND) {
51 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
52
53 if (reg) {
54 u32 phys_cpu_id = thread_to_core(*reg);
55 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
56 val = cpu_to_fdt64(val);
57 if (*reg == id) {
58 fdt_setprop_string(blob, off, "status",
59 "okay");
60 } else {
61 fdt_setprop_string(blob, off, "status",
62 "disabled");
63 }
64
65 if (hold_cores_in_reset(0)) {
66 #ifdef CONFIG_FSL_CORENET
67 /* Cores held in reset, use BRR to release */
68 enable_method = "fsl,brr-holdoff";
69 #else
70 /* Cores held in reset, use EEBPCR to release */
71 enable_method = "fsl,eebpcr-holdoff";
72 #endif
73 } else {
74 /* Cores out of reset and in a spin-loop */
75 enable_method = "spin-table";
76
77 fdt_setprop(blob, off, "cpu-release-addr",
78 &val, sizeof(val));
79 }
80
81 fdt_setprop_string(blob, off, "enable-method",
82 enable_method);
83 } else {
84 printf ("cpu NULL\n");
85 }
86 off = fdt_node_offset_by_prop_value(blob, off,
87 "device_type", "cpu", 4);
88 }
89
90 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
91 #define CONFIG_MEM_HOLE_16M 0x1000000
92 /*
93 * Extract hwconfig from environment.
94 * Search for tdm entry in hwconfig.
95 */
96 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
97 if (ret > 0)
98 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
99
100 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
101 if (tdm_hwconfig_enabled) {
102 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
103 CONFIG_MEM_HOLE_16M);
104 if (off < 0)
105 printf("Failed to reserve memory for tdm: %s\n",
106 fdt_strerror(off));
107 }
108 #endif
109
110 /* Reserve the boot page so OSes dont use it */
111 if ((u64)bootpg < memory_limit) {
112 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
113 if (off < 0)
114 printf("Failed to reserve memory for bootpg: %s\n",
115 fdt_strerror(off));
116 }
117
118 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
119 /*
120 * Reserve the default boot page so OSes dont use it.
121 * The default boot page is always mapped to bootpg above using
122 * boot page translation.
123 */
124 if (0xfffff000ull < memory_limit) {
125 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
126 if (off < 0) {
127 printf("Failed to reserve memory for 0xfffff000: %s\n",
128 fdt_strerror(off));
129 }
130 }
131 #endif
132
133 /* Reserve spin table page */
134 if (spin_tbl_addr < memory_limit) {
135 off = fdt_add_mem_rsv(blob,
136 (spin_tbl_addr & ~0xffful), 4096);
137 if (off < 0)
138 printf("Failed to reserve memory for spin table: %s\n",
139 fdt_strerror(off));
140 }
141 #ifdef CONFIG_DEEP_SLEEP
142 #ifdef CONFIG_SPL_MMC_BOOT
143 off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
144 CONFIG_SYS_MMC_U_BOOT_SIZE);
145 if (off < 0)
146 printf("Failed to reserve memory for SD deep sleep: %s\n",
147 fdt_strerror(off));
148 #elif defined(CONFIG_SPL_SPI_BOOT)
149 off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
150 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
151 if (off < 0)
152 printf("Failed to reserve memory for SPI deep sleep: %s\n",
153 fdt_strerror(off));
154 #endif
155 #endif
156 }
157 #endif
158
159 #ifdef CONFIG_SYS_FSL_CPC
ft_fixup_l3cache(void * blob,int off)160 static inline void ft_fixup_l3cache(void *blob, int off)
161 {
162 u32 line_size, num_ways, size, num_sets;
163 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
164 u32 cfg0 = in_be32(&cpc->cpccfg0);
165
166 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
167 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
168 line_size = CPC_CFG0_LINE_SZ(cfg0);
169 num_sets = size / (line_size * num_ways);
170
171 fdt_setprop(blob, off, "cache-unified", NULL, 0);
172 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
173 fdt_setprop_cell(blob, off, "cache-size", size);
174 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
175 fdt_setprop_cell(blob, off, "cache-level", 3);
176 #ifdef CONFIG_SYS_CACHE_STASHING
177 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
178 #endif
179 }
180 #else
181 #define ft_fixup_l3cache(x, y)
182 #endif
183
184 #if defined(CONFIG_L2_CACHE) || \
185 defined(CONFIG_BACKSIDE_L2_CACHE) || \
186 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
ft_fixup_l2cache_compatible(void * blob,int off)187 static inline void ft_fixup_l2cache_compatible(void *blob, int off)
188 {
189 int len;
190 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
191
192 if (cpu) {
193 char buf[40];
194
195 if (isdigit(cpu->name[0])) {
196 /* MPCxxxx, where xxxx == 4-digit number */
197 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
198 cpu->name) + 1;
199 } else {
200 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
201 len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
202 tolower(cpu->name[0]), cpu->name + 1) + 1;
203 }
204
205 /*
206 * append "cache" after the NULL character that the previous
207 * sprintf wrote. This is how a device tree stores multiple
208 * strings in a property.
209 */
210 len += sprintf(buf + len, "cache") + 1;
211
212 fdt_setprop(blob, off, "compatible", buf, len);
213 }
214 }
215 #endif
216
217 #if defined(CONFIG_L2_CACHE)
218 /* return size in kilobytes */
l2cache_size(void)219 static inline u32 l2cache_size(void)
220 {
221 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
222 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
223 u32 ver = SVR_SOC_VER(get_svr());
224
225 switch (l2siz_field) {
226 case 0x0:
227 break;
228 case 0x1:
229 if (ver == SVR_8540 || ver == SVR_8560 ||
230 ver == SVR_8541 || ver == SVR_8555)
231 return 128;
232 else
233 return 256;
234 break;
235 case 0x2:
236 if (ver == SVR_8540 || ver == SVR_8560 ||
237 ver == SVR_8541 || ver == SVR_8555)
238 return 256;
239 else
240 return 512;
241 break;
242 case 0x3:
243 return 1024;
244 break;
245 }
246
247 return 0;
248 }
249
ft_fixup_l2cache(void * blob)250 static inline void ft_fixup_l2cache(void *blob)
251 {
252 int off;
253 u32 *ph;
254
255 const u32 line_size = 32;
256 const u32 num_ways = 8;
257 const u32 size = l2cache_size() * 1024;
258 const u32 num_sets = size / (line_size * num_ways);
259
260 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
261 if (off < 0) {
262 debug("no cpu node fount\n");
263 return;
264 }
265
266 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
267
268 if (ph == NULL) {
269 debug("no next-level-cache property\n");
270 return ;
271 }
272
273 off = fdt_node_offset_by_phandle(blob, *ph);
274 if (off < 0) {
275 printf("%s: %s\n", __func__, fdt_strerror(off));
276 return ;
277 }
278
279 ft_fixup_l2cache_compatible(blob, off);
280 fdt_setprop(blob, off, "cache-unified", NULL, 0);
281 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
282 fdt_setprop_cell(blob, off, "cache-size", size);
283 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
284 fdt_setprop_cell(blob, off, "cache-level", 2);
285
286 /* we dont bother w/L3 since no platform of this type has one */
287 }
288 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
289 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
ft_fixup_l2cache(void * blob)290 static inline void ft_fixup_l2cache(void *blob)
291 {
292 int off, l2_off, l3_off = -1;
293 u32 *ph;
294 #ifdef CONFIG_BACKSIDE_L2_CACHE
295 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
296 #else
297 struct ccsr_cluster_l2 *l2cache =
298 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
299 u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
300 #endif
301 u32 size, line_size, num_ways, num_sets;
302 int has_l2 = 1;
303
304 /* P2040/P2040E has no L2, so dont set any L2 props */
305 if (SVR_SOC_VER(get_svr()) == SVR_P2040)
306 has_l2 = 0;
307
308 size = (l2cfg0 & 0x3fff) * 64 * 1024;
309 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
310 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
311 num_sets = size / (line_size * num_ways);
312
313 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
314
315 while (off != -FDT_ERR_NOTFOUND) {
316 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
317
318 if (ph == NULL) {
319 debug("no next-level-cache property\n");
320 goto next;
321 }
322
323 l2_off = fdt_node_offset_by_phandle(blob, *ph);
324 if (l2_off < 0) {
325 printf("%s: %s\n", __func__, fdt_strerror(off));
326 goto next;
327 }
328
329 if (has_l2) {
330 #ifdef CONFIG_SYS_CACHE_STASHING
331 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
332 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
333 /* Only initialize every eighth thread */
334 if (reg && !((*reg) % 8)) {
335 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
336 (*reg / 4) + 32 + 1);
337 }
338 #else
339 if (reg) {
340 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
341 (*reg * 2) + 32 + 1);
342 }
343 #endif
344 #endif
345
346 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
347 fdt_setprop_cell(blob, l2_off, "cache-block-size",
348 line_size);
349 fdt_setprop_cell(blob, l2_off, "cache-size", size);
350 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
351 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
352 ft_fixup_l2cache_compatible(blob, l2_off);
353 }
354
355 if (l3_off < 0) {
356 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
357
358 if (ph == NULL) {
359 debug("no next-level-cache property\n");
360 goto next;
361 }
362 l3_off = *ph;
363 }
364 next:
365 off = fdt_node_offset_by_prop_value(blob, off,
366 "device_type", "cpu", 4);
367 }
368 if (l3_off > 0) {
369 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
370 if (l3_off < 0) {
371 printf("%s: %s\n", __func__, fdt_strerror(off));
372 return ;
373 }
374 ft_fixup_l3cache(blob, l3_off);
375 }
376 }
377 #else
378 #define ft_fixup_l2cache(x)
379 #endif
380
ft_fixup_cache(void * blob)381 static inline void ft_fixup_cache(void *blob)
382 {
383 int off;
384
385 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
386
387 while (off != -FDT_ERR_NOTFOUND) {
388 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
389 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
390 u32 isize, iline_size, inum_sets, inum_ways;
391 u32 dsize, dline_size, dnum_sets, dnum_ways;
392
393 /* d-side config */
394 dsize = (l1cfg0 & 0x7ff) * 1024;
395 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
396 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
397 dnum_sets = dsize / (dline_size * dnum_ways);
398
399 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
400 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
401 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
402
403 #ifdef CONFIG_SYS_CACHE_STASHING
404 {
405 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
406 if (reg)
407 fdt_setprop_cell(blob, off, "cache-stash-id",
408 (*reg * 2) + 32 + 0);
409 }
410 #endif
411
412 /* i-side config */
413 isize = (l1cfg1 & 0x7ff) * 1024;
414 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
415 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
416 inum_sets = isize / (iline_size * inum_ways);
417
418 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
419 fdt_setprop_cell(blob, off, "i-cache-size", isize);
420 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
421
422 off = fdt_node_offset_by_prop_value(blob, off,
423 "device_type", "cpu", 4);
424 }
425
426 ft_fixup_l2cache(blob);
427 }
428
429
fdt_add_enet_stashing(void * fdt)430 void fdt_add_enet_stashing(void *fdt)
431 {
432 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
433
434 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
435
436 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
437 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
438 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
439 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
440 }
441
442 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
443 #ifdef CONFIG_SYS_DPAA_FMAN
ft_fixup_clks(void * blob,const char * compat,u32 offset,unsigned long freq)444 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
445 unsigned long freq)
446 {
447 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
448 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
449
450 if (off >= 0) {
451 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
452 if (off > 0)
453 printf("WARNING enable to set clock-frequency "
454 "for %s: %s\n", compat, fdt_strerror(off));
455 }
456 }
457 #endif
458
ft_fixup_dpaa_clks(void * blob)459 static void ft_fixup_dpaa_clks(void *blob)
460 {
461 sys_info_t sysinfo;
462
463 get_sys_info(&sysinfo);
464 #ifdef CONFIG_SYS_DPAA_FMAN
465 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
466 sysinfo.freq_fman[0]);
467
468 #if (CONFIG_SYS_NUM_FMAN == 2)
469 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
470 sysinfo.freq_fman[1]);
471 #endif
472 #endif
473
474 #ifdef CONFIG_SYS_DPAA_QBMAN
475 do_fixup_by_compat_u32(blob, "fsl,qman",
476 "clock-frequency", sysinfo.freq_qman, 1);
477 #endif
478
479 #ifdef CONFIG_SYS_DPAA_PME
480 do_fixup_by_compat_u32(blob, "fsl,pme",
481 "clock-frequency", sysinfo.freq_pme, 1);
482 #endif
483 }
484 #else
485 #define ft_fixup_dpaa_clks(x)
486 #endif
487
488 #ifdef CONFIG_QE
ft_fixup_qe_snum(void * blob)489 static void ft_fixup_qe_snum(void *blob)
490 {
491 unsigned int svr;
492
493 svr = mfspr(SPRN_SVR);
494 if (SVR_SOC_VER(svr) == SVR_8569) {
495 if(IS_SVR_REV(svr, 1, 0))
496 do_fixup_by_compat_u32(blob, "fsl,qe",
497 "fsl,qe-num-snums", 46, 1);
498 else
499 do_fixup_by_compat_u32(blob, "fsl,qe",
500 "fsl,qe-num-snums", 76, 1);
501 }
502 }
503 #endif
504
505 #if defined(CONFIG_ARCH_P4080)
fdt_fixup_usb(void * fdt)506 static void fdt_fixup_usb(void *fdt)
507 {
508 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
509 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
510 int off;
511
512 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
513 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
514 FSL_CORENET_RCWSR11_EC1_FM1_USB1)
515 fdt_status_disabled(fdt, off);
516
517 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
518 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
519 FSL_CORENET_RCWSR11_EC2_USB2)
520 fdt_status_disabled(fdt, off);
521 }
522 #else
523 #define fdt_fixup_usb(x)
524 #endif
525
526 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
527 defined(CONFIG_ARCH_T4160)
fdt_fixup_dma3(void * blob)528 void fdt_fixup_dma3(void *blob)
529 {
530 /* the 3rd DMA is not functional if SRIO2 is chosen */
531 int nodeoff;
532 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
533
534 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
535 #if defined(CONFIG_ARCH_T2080)
536 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
537 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
538 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
539
540 switch (srds_prtcl_s2) {
541 case 0x29:
542 case 0x2d:
543 case 0x2e:
544 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
545 u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
546 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
547 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
548
549 switch (srds_prtcl_s4) {
550 case 6:
551 case 8:
552 case 14:
553 case 16:
554 #endif
555 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
556 CONFIG_SYS_ELO3_DMA3);
557 if (nodeoff > 0)
558 fdt_status_disabled(blob, nodeoff);
559 else
560 printf("WARNING: unable to disable dma3\n");
561 break;
562 default:
563 break;
564 }
565 }
566 #else
567 #define fdt_fixup_dma3(x)
568 #endif
569
570 #if defined(CONFIG_ARCH_T1040)
571 static void fdt_fixup_l2_switch(void *blob)
572 {
573 uchar l2swaddr[6];
574 int node;
575
576 /* The l2switch node from device-tree has
577 * compatible string "vitesse-9953" */
578 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
579 if (node == -FDT_ERR_NOTFOUND)
580 /* no l2switch node has been found */
581 return;
582
583 /* Get MAC address for the l2switch from "l2switchaddr"*/
584 if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
585 printf("Warning: MAC address for l2switch not found\n");
586 memset(l2swaddr, 0, sizeof(l2swaddr));
587 }
588
589 /* Add MAC address to l2switch node */
590 fdt_setprop(blob, node, "local-mac-address", l2swaddr,
591 sizeof(l2swaddr));
592 }
593 #else
594 #define fdt_fixup_l2_switch(x)
595 #endif
596
597 void ft_cpu_setup(void *blob, bd_t *bd)
598 {
599 int off;
600 int val;
601 int len;
602 sys_info_t sysinfo;
603
604 /* delete crypto node if not on an E-processor */
605 if (!IS_E_PROCESSOR(get_svr()))
606 fdt_fixup_crypto_node(blob, 0);
607 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
608 else {
609 ccsr_sec_t __iomem *sec;
610
611 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
612 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
613 }
614 #endif
615
616 fdt_add_enet_stashing(blob);
617
618 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
619 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
620 #endif
621 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
622 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
623 1);
624 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
625 "bus-frequency", bd->bi_busfreq, 1);
626 get_sys_info(&sysinfo);
627 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
628 while (off != -FDT_ERR_NOTFOUND) {
629 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
630 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
631 fdt_setprop(blob, off, "clock-frequency", &val, 4);
632 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
633 "cpu", 4);
634 }
635 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
636 "bus-frequency", bd->bi_busfreq, 1);
637
638 #ifdef CONFIG_QE
639 ft_qe_setup(blob);
640 ft_fixup_qe_snum(blob);
641 #endif
642
643 #ifdef CONFIG_SYS_DPAA_FMAN
644 fdt_fixup_fman_firmware(blob);
645 #endif
646
647 #ifdef CONFIG_SYS_NS16550
648 do_fixup_by_compat_u32(blob, "ns16550",
649 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
650 #endif
651
652 #ifdef CONFIG_CPM2
653 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
654 "current-speed", gd->baudrate, 1);
655
656 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
657 "clock-frequency", bd->bi_brgfreq, 1);
658 #endif
659
660 #ifdef CONFIG_FSL_CORENET
661 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
662 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
663 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
664 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
665 do_fixup_by_compat_u32(blob, "fsl,mpic",
666 "clock-frequency", get_bus_freq(0)/2, 1);
667 #else
668 do_fixup_by_compat_u32(blob, "fsl,mpic",
669 "clock-frequency", get_bus_freq(0), 1);
670 #endif
671
672 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
673
674 #ifdef CONFIG_MP
675 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
676 ft_fixup_num_cores(blob);
677 #endif
678
679 ft_fixup_cache(blob);
680
681 #if defined(CONFIG_FSL_ESDHC)
682 fdt_fixup_esdhc(blob, bd);
683 #endif
684
685 ft_fixup_dpaa_clks(blob);
686
687 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
688 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
689 (u64)CONFIG_SYS_BMAN_MEM_PHYS,
690 CONFIG_SYS_BMAN_MEM_SIZE);
691 fdt_fixup_bportals(blob);
692 #endif
693
694 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
695 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
696 (u64)CONFIG_SYS_QMAN_MEM_PHYS,
697 CONFIG_SYS_QMAN_MEM_SIZE);
698
699 fdt_fixup_qportals(blob);
700 #endif
701
702 #ifdef CONFIG_SYS_SRIO
703 ft_srio_setup(blob);
704 #endif
705
706 /*
707 * system-clock = CCB clock/2
708 * Here gd->bus_clk = CCB clock
709 * We are using the system clock as 1588 Timer reference
710 * clock source select
711 */
712 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
713 "timer-frequency", gd->bus_clk/2, 1);
714
715 /*
716 * clock-freq should change to clock-frequency and
717 * flexcan-v1.0 should change to p1010-flexcan respectively
718 * in the future.
719 */
720 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
721 "clock_freq", gd->bus_clk/2, 1);
722
723 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
724 "clock-frequency", gd->bus_clk/2, 1);
725
726 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
727 "clock-frequency", gd->bus_clk/2, 1);
728
729 fdt_fixup_usb(blob);
730
731 fdt_fixup_l2_switch(blob);
732
733 fdt_fixup_dma3(blob);
734 }
735
736 /*
737 * For some CCSR devices, we only have the virtual address, not the physical
738 * address. This is because we map CCSR as a whole, so we typically don't need
739 * a macro for the physical address of any device within CCSR. In this case,
740 * we calculate the physical address of that device using it's the difference
741 * between the virtual address of the device and the virtual address of the
742 * beginning of CCSR.
743 */
744 #define CCSR_VIRT_TO_PHYS(x) \
745 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
746
747 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
748 {
749 printf("Warning: U-Boot configured %s at address %llx,\n"
750 "but the device tree has it at %llx\n", name, uaddr, daddr);
751 }
752
753 /*
754 * Verify the device tree
755 *
756 * This function compares several CONFIG_xxx macros that contain physical
757 * addresses with the corresponding nodes in the device tree, to see if
758 * the physical addresses are all correct. For example, if
759 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
760 * of the first UART. We convert this to a physical address and compare
761 * that with the physical address of the first ns16550-compatible node
762 * in the device tree. If they don't match, then we display a warning.
763 *
764 * Returns 1 on success, 0 on failure
765 */
766 int ft_verify_fdt(void *fdt)
767 {
768 uint64_t addr = 0;
769 int aliases;
770 int off;
771
772 /* First check the CCSR base address */
773 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
774 if (off > 0) {
775 int size;
776 u32 naddr;
777 const fdt32_t *prop;
778
779 naddr = fdt_address_cells(fdt, off);
780 prop = fdt_getprop(fdt, off, "ranges", &size);
781 addr = fdt_translate_address(fdt, off, prop + naddr);
782 }
783
784 if (!addr) {
785 printf("Warning: could not determine base CCSR address in "
786 "device tree\n");
787 /* No point in checking anything else */
788 return 0;
789 }
790
791 if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
792 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
793 /* No point in checking anything else */
794 return 0;
795 }
796
797 /*
798 * Check some nodes via aliases. We assume that U-Boot and the device
799 * tree enumerate the devices equally. E.g. the first serial port in
800 * U-Boot is the same as "serial0" in the device tree.
801 */
802 aliases = fdt_path_offset(fdt, "/aliases");
803 if (aliases > 0) {
804 #ifdef CONFIG_SYS_NS16550_COM1
805 if (!fdt_verify_alias_address(fdt, aliases, "serial0",
806 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
807 return 0;
808 #endif
809
810 #ifdef CONFIG_SYS_NS16550_COM2
811 if (!fdt_verify_alias_address(fdt, aliases, "serial1",
812 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
813 return 0;
814 #endif
815 }
816
817 /*
818 * The localbus node is typically a root node, even though the lbc
819 * controller is part of CCSR. If we were to put the lbc node under
820 * the SOC node, then the 'ranges' property in the lbc node would
821 * translate through the 'ranges' property of the parent SOC node, and
822 * we don't want that. Since it's a separate node, it's possible for
823 * the 'reg' property to be wrong, so check it here. For now, we
824 * only check for "fsl,elbc" nodes.
825 */
826 #ifdef CONFIG_SYS_LBC_ADDR
827 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
828 if (off > 0) {
829 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
830 if (reg) {
831 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
832
833 addr = fdt_translate_address(fdt, off, reg);
834 if (uaddr != addr) {
835 msg("the localbus", uaddr, addr);
836 return 0;
837 }
838 }
839 }
840 #endif
841
842 return 1;
843 }
844
845 void fdt_del_diu(void *blob)
846 {
847 int nodeoff = 0;
848
849 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
850 "fsl,diu")) >= 0) {
851 fdt_del_node(blob, nodeoff);
852 }
853 }
854