Searched refs:SRLG (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-06.ll | 5 ; Check the low end of the SRLG range.
14 ; Check the high end of the defined SRLG range.
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| D | shift-12.ll | 76 ; Test removal of AND mask from SRLG.
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| D | insert-05.ll | 83 ; Check that SRLG is still used if some of the high bits are known to be 0
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | shift-06.ll | 5 ; Check the low end of the SRLG range.
14 ; Check the high end of the defined SRLG range.
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| D | shift-12.ll | 76 ; Test removal of AND mask from SRLG.
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| D | insert-05.ll | 83 ; Check that SRLG is still used if some of the high bits are known to be 0
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| /external/v8/src/s390/ |
| D | simulator-s390.h | 1081 EVALUATE(SRLG);
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| D | constants-s390.h | 160 V(srlg, SRLG, 0xEB0C) /* type = RSY_A SHIFT RIGHT SINGLE LOGICAL (64) */ \
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| D | simulator-s390.cc | 1369 EvalTable[SRLG] = &Simulator::Evaluate_SRLG; in EvalTableInit()
8696 EVALUATE(SRLG) { in EVALUATE() argument
8697 DCHECK_OPCODE(SRLG); in EVALUATE()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1218 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
1741 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1368 def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>;
2181 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
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| /external/capstone/arch/SystemZ/ |
| D | SystemZGenAsmWriter.inc | 860 977278144U, // SRLG
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| D | SystemZGenDisassemblerTables.inc | 1187 /* 1414 */ MCD_OPC_Decode, 199, 6, 119, // Opcode: SRLG
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