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1; Test removal of AND operations that don't affect last 6 bits of shift amount
2; operand.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5
6; Test that AND is not removed when some lower 6 bits are not set.
7define i32 @f1(i32 %a, i32 %sh) {
8; CHECK-LABEL: f1:
9; CHECK: nil{{[lf]}} %r3, 31
10; CHECK: sll %r2, 0(%r3)
11  %and = and i32 %sh, 31
12  %shift = shl i32 %a, %and
13  ret i32 %shift
14}
15
16; Test removal of AND mask with only bottom 6 bits set.
17define i32 @f2(i32 %a, i32 %sh) {
18; CHECK-LABEL: f2:
19; CHECK-NOT: nil{{[lf]}} %r3, 63
20; CHECK: sll %r2, 0(%r3)
21  %and = and i32 %sh, 63
22  %shift = shl i32 %a, %and
23  ret i32 %shift
24}
25
26; Test removal of AND mask including but not limited to bottom 6 bits.
27define i32 @f3(i32 %a, i32 %sh) {
28; CHECK-LABEL: f3:
29; CHECK-NOT: nil{{[lf]}} %r3, 255
30; CHECK: sll %r2, 0(%r3)
31  %and = and i32 %sh, 255
32  %shift = shl i32 %a, %and
33  ret i32 %shift
34}
35
36; Test removal of AND mask from SRA.
37define i32 @f4(i32 %a, i32 %sh) {
38; CHECK-LABEL: f4:
39; CHECK-NOT: nil{{[lf]}} %r3, 63
40; CHECK: sra %r2, 0(%r3)
41  %and = and i32 %sh, 63
42  %shift = ashr i32 %a, %and
43  ret i32 %shift
44}
45
46; Test removal of AND mask from SRL.
47define i32 @f5(i32 %a, i32 %sh) {
48; CHECK-LABEL: f5:
49; CHECK-NOT: nil{{[lf]}} %r3, 63
50; CHECK: srl %r2, 0(%r3)
51  %and = and i32 %sh, 63
52  %shift = lshr i32 %a, %and
53  ret i32 %shift
54}
55
56; Test removal of AND mask from SLLG.
57define i64 @f6(i64 %a, i64 %sh) {
58; CHECK-LABEL: f6:
59; CHECK-NOT: nil{{[lf]}} %r3, 63
60; CHECK: sllg %r2, %r2, 0(%r3)
61  %and = and i64 %sh, 63
62  %shift = shl i64 %a, %and
63  ret i64 %shift
64}
65
66; Test removal of AND mask from SRAG.
67define i64 @f7(i64 %a, i64 %sh) {
68; CHECK-LABEL: f7:
69; CHECK-NOT: nil{{[lf]}} %r3, 63
70; CHECK: srag %r2, %r2, 0(%r3)
71  %and = and i64 %sh, 63
72  %shift = ashr i64 %a, %and
73  ret i64 %shift
74}
75
76; Test removal of AND mask from SRLG.
77define i64 @f8(i64 %a, i64 %sh) {
78; CHECK-LABEL: f8:
79; CHECK-NOT: nil{{[lf]}} %r3, 63
80; CHECK: srlg %r2, %r2, 0(%r3)
81  %and = and i64 %sh, 63
82  %shift = lshr i64 %a, %and
83  ret i64 %shift
84}
85
86; Test that AND with two register operands is not affected.
87define i32 @f9(i32 %a, i32 %b, i32 %sh) {
88; CHECK-LABEL: f9:
89; CHECK: nr %r3, %r4
90; CHECK: sll %r2, 0(%r3)
91  %and = and i32 %sh, %b
92  %shift = shl i32 %a, %and
93  ret i32 %shift
94}
95
96; Test that AND is not entirely removed if the result is reused.
97define i32 @f10(i32 %a, i32 %sh) {
98; CHECK-LABEL: f10:
99; CHECK: sll %r2, 0(%r3)
100; CHECK: nil{{[lf]}} %r3, 63
101; CHECK: ar %r2, %r3
102  %and = and i32 %sh, 63
103  %shift = shl i32 %a, %and
104  %reuse = add i32 %and, %shift
105  ret i32 %reuse
106}
107
108; Test that AND is not removed for i128 (which calls __ashlti3)
109define i128 @f11(i128 %a, i32 %sh) {
110; CHECK-LABEL: f11:
111; CHECK: risbg %r4, %r4, 57, 191, 0
112; CHECK: brasl %r14, __ashlti3@PLT
113  %and = and i32 %sh, 127
114  %ext = zext i32 %and to i128
115  %shift = shl i128 %a, %ext
116  ret i128 %shift
117}
118
119