Home
last modified time | relevance | path

Searched refs:ST0 (Results 1 – 25 of 63) sorted by relevance

123

/external/mesa3d/src/mesa/x86/
Dx86_xform4.S119 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
121 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
135 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
137 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
138 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
139 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
151 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
153 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
[all …]
Dx86_xform3.S119 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
121 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
135 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
137 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
138 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
139 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
222 FADDP( ST0, ST(4) ) /* F1 F2 F5 F4 */
223 FADDP( ST0, ST(2) ) /* F2 F5 F4 */
[all …]
Dx86_xform2.S119 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
121 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
272 FADDP( ST0, ST(5) ) /* F1 F2 F6 F5 F4 */
273 FADDP( ST0, ST(3) ) /* F2 F6 F5 F4 */
274 FADDP( ST0, ST(1) ) /* F6 F5 F4 */
352 FADDP( ST0, ST(2) ) /* F4 F5 */
420 FADDP( ST0, ST(3) ) /* F1 F5 F4 */
421 FADDP( ST0, ST(1) ) /* F5 F4 */
[all …]
Dx86_cliptest.S228 FMUL2( ST(1), ST0 )
231 FMUL2( ST(2), ST0 )
234 FMUL2( ST(3), ST0 )
/external/libunwind/src/x86/
Dinit.h44 c->dwarf.loc[ST0] = DWARF_REG_LOC (&c->dwarf, UNW_X86_ST0); in common_init()
45 for (i = ST0 + 1; i < DWARF_NUM_PRESERVED_REGS; ++i) in common_init()
Dunwind_i.h47 #define ST0 11 macro
DGget_save_loc.c50 case UNW_X86_ST0: loc = c->dwarf.loc[ST0]; break; in unw_get_save_loc()
DGregs.c130 loc = c->dwarf.loc[ST0]; in tdep_access_fpreg()
DGos-linux.c137 c->dwarf.loc[ST0] = DWARF_NULL_LOC; in unw_handle_signal_frame()
DGos-freebsd.c133 c->dwarf.loc[ST0] = DWARF_NULL_LOC; in unw_handle_signal_frame()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrControl.td141 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
180 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
216 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
248 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
281 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
DX86CallingConv.td53 // Long double types are always returned in ST0 (even with SSE).
54 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
59 // The X86-32 calling convention returns FP values in ST0, unless marked
66 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
DX86FloatingPoint.cpp222 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; in getSTReg()
513 MBB->addLiveIn(X86::ST0+i-1); in setupBlockStack()
843 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); in popStackAfter()
1322 unsigned DstST = MO0.getReg() - X86::ST0; in handleSpecialFP()
1323 unsigned SrcST = MO1.getReg() - X86::ST0; in handleSpecialFP()
1481 unsigned STReg = MO.getReg() - X86::ST0; in handleSpecialFP()
DX86GenRegisterInfo.inc139 ST0 = 120,
368 const unsigned ST0_Overlaps[] = { X86::ST0, 0 };
685 { "ST0", ST0_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
950 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
1206 RI->mapDwarfRegToLLVMReg(33, X86::ST0, false );
1249 RI->mapDwarfRegToLLVMReg(12, X86::ST0, false );
1284 RI->mapDwarfRegToLLVMReg(11, X86::ST0, false );
1332 RI->mapDwarfRegToLLVMReg(33, X86::ST0, true );
1375 RI->mapDwarfRegToLLVMReg(12, X86::ST0, true );
1410 RI->mapDwarfRegToLLVMReg(11, X86::ST0, true );
[all …]
DX86RegisterInfo.td146 // MMX Registers. These are actually aliased to ST0 .. ST7
217 def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>;
/external/python/cpython2/Lib/test/
Dallsans.pem10 ST0/px0zmKsYgmH8KkhfH7MNfeX9rLCpPJuXA/eo2G03tzGEPqqwQhxsb2ygv2Qs
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …P4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11 ST0 ST1 ST2 ST3 ST4 ST5…
Dinline-asm-fpstack.ll349 …es:frndint> [sideeffect] [attdialect], $0:[regdef], %ST0<imp-def,tied5>, $1:[reguse tiedto:$0], %S…
351 ; %FP0<def> = COPY %ST0
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp175 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3: in getX86RegNum()
177 return RegNo-X86::ST0; in getX86RegNum()
/external/llvm/lib/Target/X86/
DX86FloatingPoint.cpp197 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
483 MBB->addLiveIn(X86::ST0+i-1); in setupBlockStack()
805 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); in popStackAfter()
1583 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV4.td152 // ST0
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86Disassembler.cpp500 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos)); in translateFPRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86FloatingPoint.cpp206 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
842 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); in popStackAfter()
1635 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmParser.cpp426 RegNo = X86::ST0; in ParseRegister()
440 case 0: RegNo = X86::ST0; break; in ParseRegister()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc153 ST0 = 133,
1207 { X86::ST0 },
1962 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2314 { 33U, X86::ST0 },
2367 { 12U, X86::ST0 },
2412 { 11U, X86::ST0 },
2481 { 33U, X86::ST0 },
2534 { 12U, X86::ST0 },
2579 { 11U, X86::ST0 },
2657 { X86::ST0, 33U },
[all …]

123