1//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine. 11// This file describes that machine information. 12 13// 14// |===========|==================================================| 15// | PIPELINE | Instruction Classes | 16// |===========|==================================================| 17// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM | 18// |-----------|--------------------------------------------------| 19// | SLOT1 | LD ST ALU32 | 20// |-----------|--------------------------------------------------| 21// | SLOT2 | XTYPE ALU32 J JR | 22// |-----------|--------------------------------------------------| 23// | SLOT3 | XTYPE ALU32 J CR | 24// |===========|==================================================| 25 26// Functional Units. 27def SLOT0 : FuncUnit; 28def SLOT1 : FuncUnit; 29def SLOT2 : FuncUnit; 30def SLOT3 : FuncUnit; 31// Endloop is a pseudo instruction that is encoded with 2 bits in a packet 32// rather than taking an execution slot. This special unit is needed 33// to schedule an ENDLOOP with 4 other instructions. 34def SLOT_ENDLOOP: FuncUnit; 35 36// Itinerary classes. 37def PSEUDO : InstrItinClass; 38def PSEUDOM : InstrItinClass; 39// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4. 40def DUPLEX : InstrItinClass; 41def PREFIX : InstrItinClass; 42def COMPOUND_CJ_ARCHDEPSLOT : InstrItinClass; 43def COMPOUND : InstrItinClass; 44 45def ALU32_2op_tc_1_SLOT0123 : InstrItinClass; 46def ALU32_2op_tc_2early_SLOT0123 : InstrItinClass; 47def ALU32_3op_tc_2early_SLOT0123 : InstrItinClass; 48def ALU32_3op_tc_1_SLOT0123 : InstrItinClass; 49def ALU32_3op_tc_2_SLOT0123 : InstrItinClass; 50def ALU32_ADDI_tc_1_SLOT0123 : InstrItinClass; 51def ALU64_tc_1_SLOT23 : InstrItinClass; 52def ALU64_tc_1or2_SLOT23 : InstrItinClass; 53def ALU64_tc_2_SLOT23 : InstrItinClass; 54def ALU64_tc_2early_SLOT23 : InstrItinClass; 55def ALU64_tc_3x_SLOT23 : InstrItinClass; 56def CR_tc_2_SLOT3 : InstrItinClass; 57def CR_tc_2early_SLOT23 : InstrItinClass; 58def CR_tc_2early_SLOT3 : InstrItinClass; 59def CR_tc_3x_SLOT23 : InstrItinClass; 60def CR_tc_3x_SLOT3 : InstrItinClass; 61def J_tc_2early_SLOT23 : InstrItinClass; 62def J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT : InstrItinClass; 63def J_tc_2early_SLOT2 : InstrItinClass; 64def LD_tc_ld_SLOT01 : InstrItinClass; 65def LD_tc_ld_SLOT0 : InstrItinClass; 66def LD_tc_3or4stall_SLOT0 : InstrItinClass; 67def M_tc_1_SLOT23 : InstrItinClass; 68def M_tc_1or2_SLOT23 : InstrItinClass; 69def M_tc_2_SLOT23 : InstrItinClass; 70def M_tc_3_SLOT23 : InstrItinClass; 71def M_tc_3x_SLOT23 : InstrItinClass; 72def M_tc_3or4x_SLOT23 : InstrItinClass; 73def ST_tc_st_SLOT01 : InstrItinClass; 74def ST_tc_st_SLOT0 : InstrItinClass; 75def ST_tc_ld_SLOT0 : InstrItinClass; 76def ST_tc_3stall_SLOT0 : InstrItinClass; 77def S_2op_tc_1_SLOT23 : InstrItinClass; 78def S_2op_tc_2_SLOT23 : InstrItinClass; 79def S_2op_tc_2early_SLOT23 : InstrItinClass; 80def S_2op_tc_3or4x_SLOT23 : InstrItinClass; 81def S_3op_tc_1_SLOT23 : InstrItinClass; 82def S_3op_tc_1or2_SLOT23 : InstrItinClass; 83def S_3op_tc_2_SLOT23 : InstrItinClass; 84def S_3op_tc_2early_SLOT23 : InstrItinClass; 85def S_3op_tc_3_SLOT23 : InstrItinClass; 86def S_3op_tc_3x_SLOT23 : InstrItinClass; 87def NCJ_tc_3or4stall_SLOT0 : InstrItinClass; 88def V2LDST_tc_ld_SLOT01 : InstrItinClass; 89def V2LDST_tc_st_SLOT0 : InstrItinClass; 90def V2LDST_tc_st_SLOT01 : InstrItinClass; 91def V4LDST_tc_ld_SLOT01 : InstrItinClass; 92def V4LDST_tc_st_SLOT0 : InstrItinClass; 93def V4LDST_tc_st_SLOT01 : InstrItinClass; 94def J_tc_2early_SLOT0123 : InstrItinClass; 95def EXTENDER_tc_1_SLOT0123 : InstrItinClass; 96def S_3op_tc_3stall_SLOT23 : InstrItinClass; 97 98 99def HexagonItinerariesV4 : 100 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [ 101 // ALU32 102 InstrItinData<ALU32_2op_tc_1_SLOT0123 , 103 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 104 InstrItinData<ALU32_2op_tc_2early_SLOT0123, 105 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 106 InstrItinData<ALU32_3op_tc_1_SLOT0123 , 107 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 108 InstrItinData<ALU32_3op_tc_2early_SLOT0123, 109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 110 InstrItinData<ALU32_3op_tc_2_SLOT0123 , 111 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 112 InstrItinData<ALU32_ADDI_tc_1_SLOT0123 , 113 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 114 115 // ALU64 116 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 117 InstrItinData<ALU64_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 118 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 119 InstrItinData<ALU64_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 120 InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 121 122 // CR -> System 123 InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>]>, 124 InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>]>, 125 InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>]>, 126 127 // Jump (conditional/unconditional/return etc) 128 // CR 129 InstrItinData<CR_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 130 InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 131 // J 132 InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 133 // JR 134 InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>]>, 135 136 //Load 137 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 138 InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>, 139 InstrItinData<LD_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>, 140 141 // M 142 InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 143 InstrItinData<M_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 144 InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 145 InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 146 InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 147 InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 148 149 // Store 150 // ST 151 InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 152 // ST0 153 InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, 154 InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>, 155 156 // S 157 InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 158 InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 159 InstrItinData<S_2op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 160 InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 161 InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 162 InstrItinData<S_3op_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 163 InstrItinData<S_3op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 164 InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 165 InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 166 InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, 167 168 // SYS 169 InstrItinData<ST_tc_3stall_SLOT0 , [InstrStage<1, [SLOT0]>]>, 170 171 // New Value Compare Jump 172 InstrItinData<NCJ_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>, 173 174 // Mem ops - MEM_V4 175 InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, 176 InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 177 InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 178 InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, 179 InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 180 InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, 181 182 InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>, 183 184 // ENDLOOP 185 InstrItinData<J_tc_2early_SLOT0123 , [InstrStage<1, [SLOT_ENDLOOP]>]>, 186 187 // Extender/PREFIX 188 InstrItinData<EXTENDER_tc_1_SLOT0123, 189 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 190 191 InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>, 192 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 193 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 194 InstrStage<1, [SLOT2, SLOT3]>]> 195 ]>; 196 197def HexagonModelV4 : SchedMachineModel { 198 // Max issue per cycle == bundle width. 199 let IssueWidth = 4; 200 let Itineraries = HexagonItinerariesV4; 201 let LoadLatency = 1; 202 let CompleteModel = 0; 203} 204 205//===----------------------------------------------------------------------===// 206// Hexagon V4 Resource Definitions - 207//===----------------------------------------------------------------------===// 208