| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 117 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>(); in EmitFunctionBodyStart() local
119 if (STM.isAmdHsaOS()) { in EmitFunctionBodyStart()
127 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>(); in EmitFunctionEntryLabel() local
128 if (MFI->isKernel() && STM.isAmdHsaOS()) { in EmitFunctionEntryLabel()
159 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>(); in runOnMachineFunction() local
161 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { in runOnMachineFunction()
163 if (!STM.isAmdHsaOS()) { in runOnMachineFunction()
181 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { in runOnMachineFunction()
233 if (STM.dumpCode()) { in runOnMachineFunction()
253 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>(); in EmitProgramInfoR600() local
[all …]
|
| D | SILoadStoreOptimizer.cpp | 414 const SISubtarget &STM = MF.getSubtarget<SISubtarget>(); in runOnMachineFunction() local
415 if (!STM.loadStoreOptEnabled()) in runOnMachineFunction()
418 TII = STM.getInstrInfo(); in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 200 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in EmitFunctionBodyStart() local
202 if (STM.isAmdCodeObjectV2(F) && in EmitFunctionBodyStart()
261 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in EmitFunctionEntryLabel() local
262 if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(MF->getFunction())) { in EmitFunctionEntryLabel()
405 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
408 if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) { in runOnMachineFunction()
424 if (STM.isAmdPalOS()) in runOnMachineFunction()
426 else if (!STM.isAmdHsaOS()) { in runOnMachineFunction()
511 if (STM.dumpCode()) { in runOnMachineFunction()
532 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getFunctionCodeSize() local
[all …]
|
| D | R600AsmPrinter.cpp | 48 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>(); in EmitProgramInfoR600() local
49 const R600RegisterInfo *RI = STM.getRegisterInfo(); in EmitProgramInfoR600()
72 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) { in EmitProgramInfoR600()
|
| D | AMDGPUHSAMetadataStreamer.cpp | 206 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSACodeProps() local
215 HSACodeProps.mKernargSegmentSize = STM.getKernArgSegmentSize(F, in getHSACodeProps()
220 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()
225 HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled(); in getHSACodeProps()
235 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSADebugProps() local
238 if (!STM.debuggerSupported()) in getHSADebugProps()
244 if (STM.debuggerEmitPrologue()) { in getHSADebugProps()
|
| D | SILoadStoreOptimizer.cpp | 106 const GCNSubtarget *STM = nullptr; member in __anon2fce1e820111::SILoadStoreOptimizer
466 if (STM->ldsRequiresM0Init()) in read2Opcode()
472 if (STM->ldsRequiresM0Init()) in read2ST64Opcode()
562 if (STM->ldsRequiresM0Init()) in write2Opcode()
568 if (STM->ldsRequiresM0Init()) in write2ST64Opcode()
880 CI.EltSize = AMDGPU::getSMRDEncodedOffset(*STM, 4); in optimizeBlock()
942 STM = &MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
943 if (!STM->loadStoreOptEnabled()) in runOnMachineFunction()
946 TII = STM->getInstrInfo(); in runOnMachineFunction()
|
| /external/u-boot/arch/arm/mach-integrator/ |
| D | Kconfig | 33 bool "Core Module for ARM926EJ-STM"
37 bool "Core Module for ARM946E-STM"
41 bool "Core Module for ARM1136JF-STM"
|
| /external/u-boot/board/armltd/integrator/ |
| D | README | 75 ap926ejs_config Integrator Core Module for ARM926EJ-STM
76 ap946es_config Integrator Core Module for ARM946E-STM
78 cp926ejs_config Integrator Core Module for ARM926EJ-STM
79 cp946es_config Integrator Core Module for ARM946E-STM
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/ |
| D | stm-scavenging.ll | 4 ; Use STM to save the three registers
22 ; Don't use STM: there is no available register to store
|
| /external/nos/test/system-test-harness/src/test-data/NIST-CAVP/ |
| D | README | 4 AES-GCM: http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | invalid-t2PUSH-thumb.txt | 3 # SP and PC are not allowed in the register list on STM instructions in Thumb2.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | cortex-a57-misched-stm.ll | 6 ; We need second, post-ra scheduling to have STM instruction combined from single-stores
|
| D | cortex-a57-misched-stm-wrback.ll | 6 ; We need second, post-ra scheduling to have STM instruction combined from single-stores
|
| D | load-store-flags.ll | 26 ; past it to form the STM.
|
| /external/llvm/test/CodeGen/ARM/ |
| D | load-store-flags.ll | 26 ; past it to form the STM.
|
| /external/llvm/utils/TableGen/ |
| D | DAGISelMatcherEmitter.cpp | 761 } else if (const SwitchTypeMatcher *STM = dyn_cast<SwitchTypeMatcher>(M)) { in BuildHistogram() local
762 for (unsigned i = 0, e = STM->getNumCases(); i != e; ++i) in BuildHistogram()
763 BuildHistogram(STM->getCaseMatcher(i), OpcodeFreq); in BuildHistogram()
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | DAGISelMatcherEmitter.cpp | 725 } else if (const SwitchTypeMatcher *STM = dyn_cast<SwitchTypeMatcher>(M)) { in BuildHistogram() local
726 for (unsigned i = 0, e = STM->getNumCases(); i != e; ++i) in BuildHistogram()
727 BuildHistogram(STM->getCaseMatcher(i), OpcodeFreq); in BuildHistogram()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetData.cpp | 356 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap); in getStructLayout() local
357 StructLayout *&SL = (*STM)[Ty]; in getStructLayout()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | DAGISelMatcherEmitter.cpp | 934 } else if (const SwitchTypeMatcher *STM = dyn_cast<SwitchTypeMatcher>(M)) { in BuildHistogram() local
935 for (unsigned i = 0, e = STM->getNumCases(); i != e; ++i) in BuildHistogram()
936 BuildHistogram(STM->getCaseMatcher(i), OpcodeFreq); in BuildHistogram()
|
| /external/llvm/lib/IR/ |
| D | DataLayout.cpp | 560 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap); in getStructLayout() local
561 StructLayout *&SL = (*STM)[Ty]; in getStructLayout()
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-thumbv7.txt | 134 # SP and PC are not allowed in the register list on STM instructions in Thumb2.
360 # 32-bit Thumb STM instructions cannot have a writeback register which appears
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| D | DataLayout.cpp | 592 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap); in getStructLayout() local
593 StructLayout *&SL = (*STM)[Ty]; in getStructLayout()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-thumbv7.txt | 134 # SP and PC are not allowed in the register list on STM instructions in Thumb2.
360 # 32-bit Thumb STM instructions cannot have a writeback register which appears
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | thumb-diagnostics.s | 71 @ Invalid writeback and register lists for STM
|
| /external/u-boot/ |
| D | MAINTAINERS | 197 ARM STM SPEAR
204 ARM STM STM32MP
212 ARM STM STV0991
|