| /external/swiftshader/third_party/LLVM/test/CodeGen/Alpha/ |
| D | sub128.ll | 1 ;test for SUBC and SUBE expansion
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/ |
| D | addc-adde-sube-subc.ll | 5 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 208 ADDC, SUBC, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 214 ADDC, SUBC, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 223 ADDC, SUBC, enumerator
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 200 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in trySelect()
|
| D | MipsSEISelDAGToDAG.cpp | 246 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 214 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in Select()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 105 …return push_inst(compiler, SUBC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(… in emit_single_op()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 76 SUBC, // Sub with carry enumerator
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 73 SUBC, // Sub with carry enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 40 SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout). enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 234 case ISD::SUBC: return "subc"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 1388 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; in ExpandIntegerResult()
1743 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
1753 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
1834 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
2917 SDValue LowCmp = DAG.getNode(ISD::SUBC, dl, VTList, LHSLo, RHSLo); in IntegerExpandSetCCOperands()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 100 SUBC, // Sub with carry enumerator
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1846 setOperationAction(ISD::SUBC, MVT::i8, Expand); in HexagonTargetLowering()
1847 setOperationAction(ISD::SUBC, MVT::i16, Expand); in HexagonTargetLowering()
1848 setOperationAction(ISD::SUBC, MVT::i32, Expand); in HexagonTargetLowering()
1849 setOperationAction(ISD::SUBC, MVT::i64, Expand); in HexagonTargetLowering()
1938 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO, in HexagonTargetLowering()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 92 setOperationAction(ISD::SUBC, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 276 case ISD::SUBC: return "subc"; in getOperationName()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 99 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | ReleaseNotes.rst | 287 * ``ADDC``/``ADDE``/``SUBC``/``SUBE`` are now deprecated and will default to expand. Backends
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1143 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; in ExpandIntegerResult()
1519 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
1529 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); in ExpandIntRes_ADDSUB()
1578 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); in ExpandIntRes_ADDSUBC()
|
| D | DAGCombiner.cpp | 2973 if (ConstantSDNode *SUBC = in MatchRotate() local
2975 if (SUBC->getAPIntValue() == OpSizeInBits) { in MatchRotate()
2990 if (ConstantSDNode *SUBC = in MatchRotate() local
2992 if (SUBC->getAPIntValue() == OpSizeInBits) { in MatchRotate()
3020 if (ConstantSDNode *SUBC = in MatchRotate() local
3022 if (SUBC->getAPIntValue() == OpSizeInBits) { in MatchRotate()
3034 if (ConstantSDNode *SUBC = in MatchRotate() local
3036 if (SUBC->getAPIntValue() == OpSizeInBits) { in MatchRotate()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 111 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1595 setOperationAction(ISD::SUBC, MVT::i32, Custom); in SparcTargetLowering()
1601 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
2965 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3113 case ISD::SUBC: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 479 case ISD::SUBC: in Select()
702 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; in SelectADD_SUB_I64()
|