• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file implements the WebAssemblyTargetLowering class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/IR/DiagnosticInfo.h"
26 #include "llvm/IR/DiagnosticPrinter.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetOptions.h"
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "wasm-lower"
36 
WebAssemblyTargetLowering(const TargetMachine & TM,const WebAssemblySubtarget & STI)37 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
38     const TargetMachine &TM, const WebAssemblySubtarget &STI)
39     : TargetLowering(TM), Subtarget(&STI) {
40   auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
41 
42   // Booleans always contain 0 or 1.
43   setBooleanContents(ZeroOrOneBooleanContent);
44   // WebAssembly does not produce floating-point exceptions on normal floating
45   // point operations.
46   setHasFloatingPointExceptions(false);
47   // We don't know the microarchitecture here, so just reduce register pressure.
48   setSchedulingPreference(Sched::RegPressure);
49   // Tell ISel that we have a stack pointer.
50   setStackPointerRegisterToSaveRestore(
51       Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
52   // Set up the register classes.
53   addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
54   addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
55   addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
56   addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
57   // Compute derived properties from the register classes.
58   computeRegisterProperties(Subtarget->getRegisterInfo());
59 
60   setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
61   setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
62   setOperationAction(ISD::JumpTable, MVTPtr, Custom);
63   setOperationAction(ISD::BlockAddress, MVTPtr, Custom);
64   setOperationAction(ISD::BRIND, MVT::Other, Custom);
65 
66   // Take the default expansion for va_arg, va_copy, and va_end. There is no
67   // default action for va_start, so we do that custom.
68   setOperationAction(ISD::VASTART, MVT::Other, Custom);
69   setOperationAction(ISD::VAARG, MVT::Other, Expand);
70   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
71   setOperationAction(ISD::VAEND, MVT::Other, Expand);
72 
73   for (auto T : {MVT::f32, MVT::f64}) {
74     // Don't expand the floating-point types to constant pools.
75     setOperationAction(ISD::ConstantFP, T, Legal);
76     // Expand floating-point comparisons.
77     for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
78                     ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
79       setCondCodeAction(CC, T, Expand);
80     // Expand floating-point library function operators.
81     for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW,
82                     ISD::FREM, ISD::FMA})
83       setOperationAction(Op, T, Expand);
84     // Note supported floating-point library function operators that otherwise
85     // default to expand.
86     for (auto Op :
87          {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
88       setOperationAction(Op, T, Legal);
89     // Support minnan and maxnan, which otherwise default to expand.
90     setOperationAction(ISD::FMINNAN, T, Legal);
91     setOperationAction(ISD::FMAXNAN, T, Legal);
92   }
93 
94   for (auto T : {MVT::i32, MVT::i64}) {
95     // Expand unavailable integer operations.
96     for (auto Op :
97          {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
98           ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
99           ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
100           ISD::SUBE}) {
101       setOperationAction(Op, T, Expand);
102     }
103   }
104 
105   // As a special case, these operators use the type to mean the type to
106   // sign-extend from.
107   for (auto T : {MVT::i1, MVT::i8, MVT::i16, MVT::i32})
108     setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
109 
110   // Dynamic stack allocation: use the default expansion.
111   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
112   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
113   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
114 
115   setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
116   setOperationAction(ISD::CopyToReg, MVT::Other, Custom);
117 
118   // Expand these forms; we pattern-match the forms that we can handle in isel.
119   for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
120     for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
121       setOperationAction(Op, T, Expand);
122 
123   // We have custom switch handling.
124   setOperationAction(ISD::BR_JT, MVT::Other, Custom);
125 
126   // WebAssembly doesn't have:
127   //  - Floating-point extending loads.
128   //  - Floating-point truncating stores.
129   //  - i1 extending loads.
130   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
131   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
132   for (auto T : MVT::integer_valuetypes())
133     for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
134       setLoadExtAction(Ext, T, MVT::i1, Promote);
135 
136   // Trap lowers to wasm unreachable
137   setOperationAction(ISD::TRAP, MVT::Other, Legal);
138 }
139 
createFastISel(FunctionLoweringInfo & FuncInfo,const TargetLibraryInfo * LibInfo) const140 FastISel *WebAssemblyTargetLowering::createFastISel(
141     FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
142   return WebAssembly::createFastISel(FuncInfo, LibInfo);
143 }
144 
isOffsetFoldingLegal(const GlobalAddressSDNode *) const145 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
146     const GlobalAddressSDNode * /*GA*/) const {
147   // All offsets can be folded.
148   return true;
149 }
150 
getScalarShiftAmountTy(const DataLayout &,EVT VT) const151 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
152                                                       EVT VT) const {
153   unsigned BitWidth = NextPowerOf2(VT.getSizeInBits() - 1);
154   if (BitWidth > 1 && BitWidth < 8) BitWidth = 8;
155 
156   if (BitWidth > 64) {
157     // The shift will be lowered to a libcall, and compiler-rt libcalls expect
158     // the count to be an i32.
159     BitWidth = 32;
160     assert(BitWidth >= Log2_32_Ceil(VT.getSizeInBits()) &&
161            "32-bit shift counts ought to be enough for anyone");
162   }
163 
164   MVT Result = MVT::getIntegerVT(BitWidth);
165   assert(Result != MVT::INVALID_SIMPLE_VALUE_TYPE &&
166          "Unable to represent scalar shift amount type");
167   return Result;
168 }
169 
getTargetNodeName(unsigned Opcode) const170 const char *WebAssemblyTargetLowering::getTargetNodeName(
171     unsigned Opcode) const {
172   switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
173     case WebAssemblyISD::FIRST_NUMBER:
174       break;
175 #define HANDLE_NODETYPE(NODE) \
176   case WebAssemblyISD::NODE:  \
177     return "WebAssemblyISD::" #NODE;
178 #include "WebAssemblyISD.def"
179 #undef HANDLE_NODETYPE
180   }
181   return nullptr;
182 }
183 
184 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const185 WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
186     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
187   // First, see if this is a constraint that directly corresponds to a
188   // WebAssembly register class.
189   if (Constraint.size() == 1) {
190     switch (Constraint[0]) {
191       case 'r':
192         assert(VT != MVT::iPTR && "Pointer MVT not expected here");
193         if (VT.isInteger() && !VT.isVector()) {
194           if (VT.getSizeInBits() <= 32)
195             return std::make_pair(0U, &WebAssembly::I32RegClass);
196           if (VT.getSizeInBits() <= 64)
197             return std::make_pair(0U, &WebAssembly::I64RegClass);
198         }
199         break;
200       default:
201         break;
202     }
203   }
204 
205   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
206 }
207 
isCheapToSpeculateCttz() const208 bool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
209   // Assume ctz is a relatively cheap operation.
210   return true;
211 }
212 
isCheapToSpeculateCtlz() const213 bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
214   // Assume clz is a relatively cheap operation.
215   return true;
216 }
217 
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS) const218 bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
219                                                       const AddrMode &AM,
220                                                       Type *Ty,
221                                                       unsigned AS) const {
222   // WebAssembly offsets are added as unsigned without wrapping. The
223   // isLegalAddressingMode gives us no way to determine if wrapping could be
224   // happening, so we approximate this by accepting only non-negative offsets.
225   if (AM.BaseOffs < 0) return false;
226 
227   // WebAssembly has no scale register operands.
228   if (AM.Scale != 0) return false;
229 
230   // Everything else is legal.
231   return true;
232 }
233 
allowsMisalignedMemoryAccesses(EVT,unsigned,unsigned,bool * Fast) const234 bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses(
235     EVT /*VT*/, unsigned /*AddrSpace*/, unsigned /*Align*/, bool *Fast) const {
236   // WebAssembly supports unaligned accesses, though it should be declared
237   // with the p2align attribute on loads and stores which do so, and there
238   // may be a performance impact. We tell LLVM they're "fast" because
239   // for the kinds of things that LLVM uses this for (merging adjacent stores
240   // of constants, etc.), WebAssembly implementations will either want the
241   // unaligned access or they'll split anyway.
242   if (Fast) *Fast = true;
243   return true;
244 }
245 
isIntDivCheap(EVT VT,AttributeSet Attr) const246 bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
247   // The current thinking is that wasm engines will perform this optimization,
248   // so we can save on code size.
249   return true;
250 }
251 
252 //===----------------------------------------------------------------------===//
253 // WebAssembly Lowering private implementation.
254 //===----------------------------------------------------------------------===//
255 
256 //===----------------------------------------------------------------------===//
257 // Lowering Code
258 //===----------------------------------------------------------------------===//
259 
fail(const SDLoc & DL,SelectionDAG & DAG,const char * msg)260 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *msg) {
261   MachineFunction &MF = DAG.getMachineFunction();
262   DAG.getContext()->diagnose(
263       DiagnosticInfoUnsupported(*MF.getFunction(), msg, DL.getDebugLoc()));
264 }
265 
266 // Test whether the given calling convention is supported.
CallingConvSupported(CallingConv::ID CallConv)267 static bool CallingConvSupported(CallingConv::ID CallConv) {
268   // We currently support the language-independent target-independent
269   // conventions. We don't yet have a way to annotate calls with properties like
270   // "cold", and we don't have any call-clobbered registers, so these are mostly
271   // all handled the same.
272   return CallConv == CallingConv::C || CallConv == CallingConv::Fast ||
273          CallConv == CallingConv::Cold ||
274          CallConv == CallingConv::PreserveMost ||
275          CallConv == CallingConv::PreserveAll ||
276          CallConv == CallingConv::CXX_FAST_TLS;
277 }
278 
LowerCall(CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const279 SDValue WebAssemblyTargetLowering::LowerCall(
280     CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {
281   SelectionDAG &DAG = CLI.DAG;
282   SDLoc DL = CLI.DL;
283   SDValue Chain = CLI.Chain;
284   SDValue Callee = CLI.Callee;
285   MachineFunction &MF = DAG.getMachineFunction();
286   auto Layout = MF.getDataLayout();
287 
288   CallingConv::ID CallConv = CLI.CallConv;
289   if (!CallingConvSupported(CallConv))
290     fail(DL, DAG,
291          "WebAssembly doesn't support language-specific or target-specific "
292          "calling conventions yet");
293   if (CLI.IsPatchPoint)
294     fail(DL, DAG, "WebAssembly doesn't support patch point yet");
295 
296   // WebAssembly doesn't currently support explicit tail calls. If they are
297   // required, fail. Otherwise, just disable them.
298   if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
299        MF.getTarget().Options.GuaranteedTailCallOpt) ||
300       (CLI.CS && CLI.CS->isMustTailCall()))
301     fail(DL, DAG, "WebAssembly doesn't support tail call yet");
302   CLI.IsTailCall = false;
303 
304   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
305   if (Ins.size() > 1)
306     fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
307 
308   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
309   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
310   for (unsigned i = 0; i < Outs.size(); ++i) {
311     const ISD::OutputArg &Out = Outs[i];
312     SDValue &OutVal = OutVals[i];
313     if (Out.Flags.isNest())
314       fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
315     if (Out.Flags.isInAlloca())
316       fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
317     if (Out.Flags.isInConsecutiveRegs())
318       fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
319     if (Out.Flags.isInConsecutiveRegsLast())
320       fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
321     if (Out.Flags.isByVal() && Out.Flags.getByValSize() != 0) {
322       auto *MFI = MF.getFrameInfo();
323       int FI = MFI->CreateStackObject(Out.Flags.getByValSize(),
324                                       Out.Flags.getByValAlign(),
325                                       /*isSS=*/false);
326       SDValue SizeNode =
327           DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32);
328       SDValue FINode = DAG.getFrameIndex(FI, getPointerTy(Layout));
329       Chain = DAG.getMemcpy(
330           Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getByValAlign(),
331           /*isVolatile*/ false, /*AlwaysInline=*/false,
332           /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo());
333       OutVal = FINode;
334     }
335   }
336 
337   bool IsVarArg = CLI.IsVarArg;
338   unsigned NumFixedArgs = CLI.NumFixedArgs;
339 
340   auto PtrVT = getPointerTy(Layout);
341 
342   // Analyze operands of the call, assigning locations to each operand.
343   SmallVector<CCValAssign, 16> ArgLocs;
344   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
345 
346   if (IsVarArg) {
347     // Outgoing non-fixed arguments are placed in a buffer. First
348     // compute their offsets and the total amount of buffer space needed.
349     for (SDValue Arg :
350          make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
351       EVT VT = Arg.getValueType();
352       assert(VT != MVT::iPTR && "Legalized args should be concrete");
353       Type *Ty = VT.getTypeForEVT(*DAG.getContext());
354       unsigned Offset = CCInfo.AllocateStack(Layout.getTypeAllocSize(Ty),
355                                              Layout.getABITypeAlignment(Ty));
356       CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
357                                         Offset, VT.getSimpleVT(),
358                                         CCValAssign::Full));
359     }
360   }
361 
362   unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
363 
364   SDValue FINode;
365   if (IsVarArg && NumBytes) {
366     // For non-fixed arguments, next emit stores to store the argument values
367     // to the stack buffer at the offsets computed above.
368     int FI = MF.getFrameInfo()->CreateStackObject(NumBytes,
369                                                   Layout.getStackAlignment(),
370                                                   /*isSS=*/false);
371     unsigned ValNo = 0;
372     SmallVector<SDValue, 8> Chains;
373     for (SDValue Arg :
374          make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
375       assert(ArgLocs[ValNo].getValNo() == ValNo &&
376              "ArgLocs should remain in order and only hold varargs args");
377       unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
378       FINode = DAG.getFrameIndex(FI, getPointerTy(Layout));
379       SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode,
380                                 DAG.getConstant(Offset, DL, PtrVT));
381       Chains.push_back(DAG.getStore(
382           Chain, DL, Arg, Add,
383           MachinePointerInfo::getFixedStack(MF, FI, Offset), false, false, 0));
384     }
385     if (!Chains.empty())
386       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
387   } else if (IsVarArg) {
388     FINode = DAG.getIntPtrConstant(0, DL);
389   }
390 
391   // Compute the operands for the CALLn node.
392   SmallVector<SDValue, 16> Ops;
393   Ops.push_back(Chain);
394   Ops.push_back(Callee);
395 
396   // Add all fixed arguments. Note that for non-varargs calls, NumFixedArgs
397   // isn't reliable.
398   Ops.append(OutVals.begin(),
399              IsVarArg ? OutVals.begin() + NumFixedArgs : OutVals.end());
400   // Add a pointer to the vararg buffer.
401   if (IsVarArg) Ops.push_back(FINode);
402 
403   SmallVector<EVT, 8> InTys;
404   for (const auto &In : Ins) {
405     assert(!In.Flags.isByVal() && "byval is not valid for return values");
406     assert(!In.Flags.isNest() && "nest is not valid for return values");
407     if (In.Flags.isInAlloca())
408       fail(DL, DAG, "WebAssembly hasn't implemented inalloca return values");
409     if (In.Flags.isInConsecutiveRegs())
410       fail(DL, DAG, "WebAssembly hasn't implemented cons regs return values");
411     if (In.Flags.isInConsecutiveRegsLast())
412       fail(DL, DAG,
413            "WebAssembly hasn't implemented cons regs last return values");
414     // Ignore In.getOrigAlign() because all our arguments are passed in
415     // registers.
416     InTys.push_back(In.VT);
417   }
418   InTys.push_back(MVT::Other);
419   SDVTList InTyList = DAG.getVTList(InTys);
420   SDValue Res =
421       DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
422                   DL, InTyList, Ops);
423   if (Ins.empty()) {
424     Chain = Res;
425   } else {
426     InVals.push_back(Res);
427     Chain = Res.getValue(1);
428   }
429 
430   return Chain;
431 }
432 
CanLowerReturn(CallingConv::ID,MachineFunction &,bool,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext &) const433 bool WebAssemblyTargetLowering::CanLowerReturn(
434     CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
435     const SmallVectorImpl<ISD::OutputArg> &Outs,
436     LLVMContext & /*Context*/) const {
437   // WebAssembly can't currently handle returning tuples.
438   return Outs.size() <= 1;
439 }
440 
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const441 SDValue WebAssemblyTargetLowering::LowerReturn(
442     SDValue Chain, CallingConv::ID CallConv, bool /*IsVarArg*/,
443     const SmallVectorImpl<ISD::OutputArg> &Outs,
444     const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
445     SelectionDAG &DAG) const {
446   assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
447   if (!CallingConvSupported(CallConv))
448     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
449 
450   SmallVector<SDValue, 4> RetOps(1, Chain);
451   RetOps.append(OutVals.begin(), OutVals.end());
452   Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
453 
454   // Record the number and types of the return values.
455   for (const ISD::OutputArg &Out : Outs) {
456     assert(!Out.Flags.isByVal() && "byval is not valid for return values");
457     assert(!Out.Flags.isNest() && "nest is not valid for return values");
458     assert(Out.IsFixed && "non-fixed return value is not valid");
459     if (Out.Flags.isInAlloca())
460       fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
461     if (Out.Flags.isInConsecutiveRegs())
462       fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
463     if (Out.Flags.isInConsecutiveRegsLast())
464       fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
465   }
466 
467   return Chain;
468 }
469 
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const470 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
471     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
472     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
473     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
474   MachineFunction &MF = DAG.getMachineFunction();
475   auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
476 
477   if (!CallingConvSupported(CallConv))
478     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
479 
480   // Set up the incoming ARGUMENTS value, which serves to represent the liveness
481   // of the incoming values before they're represented by virtual registers.
482   MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
483 
484   for (const ISD::InputArg &In : Ins) {
485     if (In.Flags.isInAlloca())
486       fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
487     if (In.Flags.isNest())
488       fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
489     if (In.Flags.isInConsecutiveRegs())
490       fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
491     if (In.Flags.isInConsecutiveRegsLast())
492       fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
493     // Ignore In.getOrigAlign() because all our arguments are passed in
494     // registers.
495     InVals.push_back(
496         In.Used
497             ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
498                           DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
499             : DAG.getUNDEF(In.VT));
500 
501     // Record the number and types of arguments.
502     MFI->addParam(In.VT);
503   }
504 
505   // Varargs are copied into a buffer allocated by the caller, and a pointer to
506   // the buffer is passed as an argument.
507   if (IsVarArg) {
508     MVT PtrVT = getPointerTy(MF.getDataLayout());
509     unsigned VarargVreg =
510         MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));
511     MFI->setVarargBufferVreg(VarargVreg);
512     Chain = DAG.getCopyToReg(
513         Chain, DL, VarargVreg,
514         DAG.getNode(WebAssemblyISD::ARGUMENT, DL, PtrVT,
515                     DAG.getTargetConstant(Ins.size(), DL, MVT::i32)));
516     MFI->addParam(PtrVT);
517   }
518 
519   return Chain;
520 }
521 
522 //===----------------------------------------------------------------------===//
523 //  Custom lowering hooks.
524 //===----------------------------------------------------------------------===//
525 
LowerOperation(SDValue Op,SelectionDAG & DAG) const526 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
527                                                   SelectionDAG &DAG) const {
528   SDLoc DL(Op);
529   switch (Op.getOpcode()) {
530     default:
531       llvm_unreachable("unimplemented operation lowering");
532       return SDValue();
533     case ISD::FrameIndex:
534       return LowerFrameIndex(Op, DAG);
535     case ISD::GlobalAddress:
536       return LowerGlobalAddress(Op, DAG);
537     case ISD::ExternalSymbol:
538       return LowerExternalSymbol(Op, DAG);
539     case ISD::JumpTable:
540       return LowerJumpTable(Op, DAG);
541     case ISD::BR_JT:
542       return LowerBR_JT(Op, DAG);
543     case ISD::VASTART:
544       return LowerVASTART(Op, DAG);
545     case ISD::BlockAddress:
546     case ISD::BRIND:
547       fail(DL, DAG, "WebAssembly hasn't implemented computed gotos");
548       return SDValue();
549     case ISD::RETURNADDR: // Probably nothing meaningful can be returned here.
550       fail(DL, DAG, "WebAssembly hasn't implemented __builtin_return_address");
551       return SDValue();
552     case ISD::FRAMEADDR:
553       return LowerFRAMEADDR(Op, DAG);
554     case ISD::CopyToReg:
555       return LowerCopyToReg(Op, DAG);
556   }
557 }
558 
LowerCopyToReg(SDValue Op,SelectionDAG & DAG) const559 SDValue WebAssemblyTargetLowering::LowerCopyToReg(SDValue Op,
560                                                   SelectionDAG &DAG) const {
561   SDValue Src = Op.getOperand(2);
562   if (isa<FrameIndexSDNode>(Src.getNode())) {
563     // CopyToReg nodes don't support FrameIndex operands. Other targets select
564     // the FI to some LEA-like instruction, but since we don't have that, we
565     // need to insert some kind of instruction that can take an FI operand and
566     // produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy
567     // copy_local between Op and its FI operand.
568     SDValue Chain = Op.getOperand(0);
569     SDLoc DL(Op);
570     unsigned Reg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
571     EVT VT = Src.getValueType();
572     SDValue Copy(
573         DAG.getMachineNode(VT == MVT::i32 ? WebAssembly::COPY_LOCAL_I32
574                                           : WebAssembly::COPY_LOCAL_I64,
575                            DL, VT, Src),
576         0);
577     return Op.getNode()->getNumValues() == 1
578                ? DAG.getCopyToReg(Chain, DL, Reg, Copy)
579                : DAG.getCopyToReg(Chain, DL, Reg, Copy, Op.getNumOperands() == 4
580                                                             ? Op.getOperand(3)
581                                                             : SDValue());
582   }
583   return SDValue();
584 }
585 
LowerFrameIndex(SDValue Op,SelectionDAG & DAG) const586 SDValue WebAssemblyTargetLowering::LowerFrameIndex(SDValue Op,
587                                                    SelectionDAG &DAG) const {
588   int FI = cast<FrameIndexSDNode>(Op)->getIndex();
589   return DAG.getTargetFrameIndex(FI, Op.getValueType());
590 }
591 
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const592 SDValue WebAssemblyTargetLowering::LowerFRAMEADDR(SDValue Op,
593                                                   SelectionDAG &DAG) const {
594   // Non-zero depths are not supported by WebAssembly currently. Use the
595   // legalizer's default expansion, which is to return 0 (what this function is
596   // documented to do).
597   if (Op.getConstantOperandVal(0) > 0)
598     return SDValue();
599 
600   DAG.getMachineFunction().getFrameInfo()->setFrameAddressIsTaken(true);
601   EVT VT = Op.getValueType();
602   unsigned FP =
603       Subtarget->getRegisterInfo()->getFrameRegister(DAG.getMachineFunction());
604   return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), FP, VT);
605 }
606 
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const607 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
608                                                       SelectionDAG &DAG) const {
609   SDLoc DL(Op);
610   const auto *GA = cast<GlobalAddressSDNode>(Op);
611   EVT VT = Op.getValueType();
612   assert(GA->getTargetFlags() == 0 &&
613          "Unexpected target flags on generic GlobalAddressSDNode");
614   if (GA->getAddressSpace() != 0)
615     fail(DL, DAG, "WebAssembly only expects the 0 address space");
616   return DAG.getNode(
617       WebAssemblyISD::Wrapper, DL, VT,
618       DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT, GA->getOffset()));
619 }
620 
LowerExternalSymbol(SDValue Op,SelectionDAG & DAG) const621 SDValue WebAssemblyTargetLowering::LowerExternalSymbol(
622     SDValue Op, SelectionDAG &DAG) const {
623   SDLoc DL(Op);
624   const auto *ES = cast<ExternalSymbolSDNode>(Op);
625   EVT VT = Op.getValueType();
626   assert(ES->getTargetFlags() == 0 &&
627          "Unexpected target flags on generic ExternalSymbolSDNode");
628   // Set the TargetFlags to 0x1 which indicates that this is a "function"
629   // symbol rather than a data symbol. We do this unconditionally even though
630   // we don't know anything about the symbol other than its name, because all
631   // external symbols used in target-independent SelectionDAG code are for
632   // functions.
633   return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
634                      DAG.getTargetExternalSymbol(ES->getSymbol(), VT,
635                                                  /*TargetFlags=*/0x1));
636 }
637 
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const638 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
639                                                   SelectionDAG &DAG) const {
640   // There's no need for a Wrapper node because we always incorporate a jump
641   // table operand into a BR_TABLE instruction, rather than ever
642   // materializing it in a register.
643   const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
644   return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
645                                 JT->getTargetFlags());
646 }
647 
LowerBR_JT(SDValue Op,SelectionDAG & DAG) const648 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
649                                               SelectionDAG &DAG) const {
650   SDLoc DL(Op);
651   SDValue Chain = Op.getOperand(0);
652   const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
653   SDValue Index = Op.getOperand(2);
654   assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
655 
656   SmallVector<SDValue, 8> Ops;
657   Ops.push_back(Chain);
658   Ops.push_back(Index);
659 
660   MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
661   const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
662 
663   // Add an operand for each case.
664   for (auto MBB : MBBs) Ops.push_back(DAG.getBasicBlock(MBB));
665 
666   // TODO: For now, we just pick something arbitrary for a default case for now.
667   // We really want to sniff out the guard and put in the real default case (and
668   // delete the guard).
669   Ops.push_back(DAG.getBasicBlock(MBBs[0]));
670 
671   return DAG.getNode(WebAssemblyISD::BR_TABLE, DL, MVT::Other, Ops);
672 }
673 
LowerVASTART(SDValue Op,SelectionDAG & DAG) const674 SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
675                                                 SelectionDAG &DAG) const {
676   SDLoc DL(Op);
677   EVT PtrVT = getPointerTy(DAG.getMachineFunction().getDataLayout());
678 
679   auto *MFI = DAG.getMachineFunction().getInfo<WebAssemblyFunctionInfo>();
680   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
681 
682   SDValue ArgN = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
683                                     MFI->getVarargBufferVreg(), PtrVT);
684   return DAG.getStore(Op.getOperand(0), DL, ArgN, Op.getOperand(1),
685                       MachinePointerInfo(SV), false, false, 0);
686 }
687 
688 //===----------------------------------------------------------------------===//
689 //                          WebAssembly Optimization Hooks
690 //===----------------------------------------------------------------------===//
691