| /external/swiftshader/third_party/LLVM/test/CodeGen/Alpha/ |
| D | sub128.ll | 1 ;test for SUBC and SUBE expansion
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 194 case ISD::SUBE: in trySelect()
200 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in trySelect()
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| D | MipsSEISelDAGToDAG.cpp | 246 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
732 case ISD::SUBE: { in trySelect()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/ |
| D | addc-adde-sube-subc.ll | 5 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 127 case ISD::SUBE: in isdToLanaiAluCode()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 127 case ISD::SUBE: in isdToLanaiAluCode()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 209 case ISD::SUBE: in Select()
214 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in Select()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 217 ADDE, SUBE, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 223 ADDE, SUBE, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 232 ADDE, SUBE, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 99 setOperationAction(ISD::SUBE, MVT::i32, Custom); in BlackfinTargetLowering()
472 case ISD::SUBE: return LowerADDE(Op, DAG); in LowerOperation()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 77 SUBE, // Sub using carry enumerator
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 74 SUBE, // Sub using carry enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 235 case ISD::SUBE: return "sube"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 1391 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; in ExpandIntegerResult()
1755 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
1836 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
3003 SDValue LowCmp = DAG.getNode(ISD::SUBE, dl, VTList, LHSLo, RHSLo, Carry); in ExpandIntOp_SETCCE()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 101 SUBE, // Sub using carry enumerator
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 93 setOperationAction(ISD::SUBE, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 277 case ISD::SUBE: return "sube"; in getOperationName()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 100 ISD::SUBE}) { in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1596 setOperationAction(ISD::SUBE, MVT::i32, Custom); in SparcTargetLowering()
1602 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
2965 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
2966 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3114 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | ReleaseNotes.rst | 287 * ``ADDC``/``ADDE``/``SUBC``/``SUBE`` are now deprecated and will default to expand. Backends
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1838 setOperationAction(ISD::SUBE, MVT::i8, Expand); in HexagonTargetLowering()
1839 setOperationAction(ISD::SUBE, MVT::i16, Expand); in HexagonTargetLowering()
1840 setOperationAction(ISD::SUBE, MVT::i32, Expand); in HexagonTargetLowering()
1841 setOperationAction(ISD::SUBE, MVT::i64, Expand); in HexagonTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 112 ISD::SUBE}) { in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1616 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
2931 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
2932 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3080 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 480 case ISD::SUBE: { in Select()
700 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); in SelectADD_SUB_I64()
|