| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | unaligned-memops.ll | 17 ; MIPS: SWL [[LWR]], [[COPY]], 0 :: (store 4 into %ir.b, align 1)
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| D | unaligned-memops-mapping.mir | 62 SWL %4, %1, 0 :: (store 4 into %ir.b, align 1)
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 232 case Mips::SWL: in isBasePlusOffsetMemoryAccess()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 241 case Mips::SWL: in isBasePlusOffsetMemoryAccess()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 467 SWL = ((5U << 3) + 2) << kOpcodeShift, enumerator
1272 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SWR) |
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| D | disasm-mips.cc | 1938 case SWL: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 2290 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); in swl()
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| D | simulator-mips.cc | 6706 case SWL: { in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 443 SWL = ((5U << 3) + 2) << kOpcodeShift, enumerator
1307 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SD) |
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| D | disasm-mips64.cc | 2215 case SWL: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 2444 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); in swl()
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| D | simulator-mips64.cc | 6984 case SWL: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 204 SWL, enumerator
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| D | MipsISelLowering.cpp | 149 case MipsISD::SWL: return "MipsISD::SWL"; in getTargetNodeName()
2356 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, in lowerUnalignedIntStore() local
2358 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
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| D | MipsInstrInfo.td | 136 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
1771 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 250 SWL, enumerator
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| D | MipsISelLowering.cpp | 231 case MipsISD::SWL: return "MipsISD::SWL"; in getTargetNodeName()
2549 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, in lowerUnalignedIntStore() local
2551 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
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| D | MipsScheduleP5600.td | 131 SBE, SHE, SWE, SCE, SWL, SWR, SWLE, SWRE)>;
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| D | MipsInstrInfo.td | 143 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
2123 def SWL : MMRel, StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 720 {DBGFIELD("SWL") 1, false, false, 17, 2, 1, 1, 0, 0}, // #445
1740 {DBGFIELD("SWL") 1, false, false, 46, 3, 1, 1, 0, 0}, // #445
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| D | MipsGenMCCodeEmitter.inc | 2501 UINT64_C(2818572288), // SWL
5661 case Mips::SWL:
10227 …e_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SWL = 2488
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| D | MipsGenInstrInfo.inc | 2503 SWL = 2488,
3102 SWL = 445,
6548 …1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2488 = SWL
10253 { Mips::SWL, Mips::SWL, Mips::SWL_MM },
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| D | MipsGenAsmWriter.inc | 3716 25188612U, // SWL
6347 0U, // SWL
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1600 12605056U, // SWL
3314 0U, // SWL
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4292 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; in expandUxw()
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