| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | invalid-SXTB-arm.txt | 9 # A8.6.223 SXTB
|
| D | thumb1.txt | 494 # SXTB/SXTH
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 45 SXTB, enumerator
64 case AArch64_AM::SXTB: return "sxtb"; in getShiftExtendName()
131 case 4: return AArch64_AM::SXTB; in getExtendType()
158 case AArch64_AM::SXTB: return 4; break; in getExtendEncoding()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 45 SXTB, enumerator
64 case AArch64_AM::SXTB: return "sxtb"; in getShiftExtendName()
131 case 4: return AArch64_AM::SXTB; in getExtendType()
158 case AArch64_AM::SXTB: return 4; break; in getExtendEncoding()
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-t32.json | 54 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1
55 // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-ror-amount-a32.json | 32 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| D | cond-rd-operand-rn-ror-amount-t32.json | 32 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-a32.json | 46 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
|
| D | invalid-armv7.txt | 330 # A8.6.223 SXTB
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
|
| D | invalid-armv7.txt | 330 # A8.6.223 SXTB
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 364 SXTB, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 405 SXTB, enumerator
|
| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 356 VIXL_CHECK(!Operand(w12, SXTB).IsPlainRegister()); in TEST()
|
| D | test-assembler-aarch64.cc | 445 __ Add(sp, sp, Operand(x17, SXTB)); in TEST()
492 __ Mvn(x11, Operand(x2, SXTB, 1)); in TEST()
667 __ Mov(x24, Operand(x13, SXTB, 1)); in TEST()
721 __ Mov(w20, Operand(w11, SXTB, 1)); in TEST()
805 __ Orr(w10, w0, Operand(w1, SXTB)); in TEST()
899 __ Orn(w10, w0, Operand(w1, SXTB)); in TEST()
966 __ And(w10, w0, Operand(w1, SXTB)); in TEST()
1104 __ Bic(w10, w0, Operand(w1, SXTB)); in TEST()
1228 __ Eor(w10, w0, Operand(w1, SXTB)); in TEST()
1295 __ Eon(w10, w0, Operand(w1, SXTB)); in TEST()
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 587 @ SXTB/SXTH
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 239 return Size == 8 ? ARM::SXTB : ARM::SXTH; in selectSimpleExtOpc()
|
| D | ARMFastISel.cpp | 2667 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2912 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 173 #define SXTB 0xb240 macro
758 return push_inst16(compiler, SXTB | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| D | sljitNativeARM_32.c | 131 #define SXTB 0xe6af0070 macro
1050 return push_inst(compiler, (op == SLJIT_MOV_U8 ? UXTB : SXTB) | RD(dst) | RM(src2)); in emit_single_op()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2641 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2886 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
|
| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 127 return Operand(InputRegister32(index), SXTB); in InputOperand2_32()
157 return Operand(InputRegister64(index), SXTB); in InputOperand2_64()
|