1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27// Test description for instructions of the following form: 28// MNEMONIC{<c>}.W <Rd>, <Rn>, ROR #<amount> 29 30{ 31 "mnemonics": [ 32 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 33 "Sxtb16", // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1 34 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 35 "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 36 "Uxtb16", // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1 37 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 38 ], 39 "description": { 40 "operands": [ 41 { 42 "name": "cond", 43 "type": "Condition" 44 }, 45 { 46 "name": "rd", 47 "type": "AllRegistersButPC" 48 }, 49 { 50 "name": "op", 51 "wrapper": "Operand", 52 "operands": [ 53 { 54 "name": "rn", 55 "type": "AllRegistersButPC" 56 }, 57 { 58 "name": "ror", 59 "type": "ShiftROR" 60 }, 61 { 62 "name": "amount", 63 "type": "ShiftRotationAmountX8" 64 } 65 ] 66 } 67 ], 68 "inputs": [ 69 { 70 "name": "apsr", 71 "type": "NZCV" 72 }, 73 { 74 "name": "rd", 75 "type": "Register" 76 }, 77 { 78 "name": "rn", 79 "type": "Register" 80 } 81 ] 82 }, 83 "test-files": [ 84 { 85 "type": "assembler", 86 "test-cases": [ 87 { 88 "name": "Operands", 89 "operands": [ 90 "cond", "rd", "rn", "ror", "amount" 91 ], 92 "operand-filter": "cond == 'al'" 93 } 94 ] 95 }, 96 { 97 "type": "simulator", 98 "test-cases": [ 99 { 100 "name": "Condition", 101 "operands": [ 102 "cond" 103 ], 104 "inputs": [ 105 "apsr" 106 ] 107 }, 108 // Test combinations of registers values with rd == rn. 109 { 110 "name": "RdIsRn", 111 "operands": [ 112 "rd", "rn" 113 ], 114 "inputs": [ 115 "rd", "rn" 116 ], 117 "operand-filter": "rd == rn", 118 "input-filter": "rd == rn" 119 }, 120 // Test combinations of registers values. 121 { 122 "name": "RdIsNotRn", 123 "operands": [ 124 "rd", "rn" 125 ], 126 "inputs": [ 127 "rd", "rn" 128 ], 129 "operand-filter": "rd != rn", 130 "operand-limit": 10, 131 "input-limit": 200 132 }, 133 // Test combinations of rotation amounts. 134 { 135 "name": "Rotations", 136 "operands": [ 137 "rd", "rn", "ror", "amount" 138 ], 139 "inputs": [ 140 "rn" 141 ], 142 // Specify exactly what registers to use in this test to make sure 143 // that they are different. It makes the execution trace more 144 // understandable. 145 "operand-filter": "rd == 'r0' and rn == 'r1'" 146 } 147 ] 148 } 149 ] 150} 151