| /external/v8/src/regexp/arm64/ |
| D | regexp-macro-assembler-arm64.cc | 241 Operand(current_input_offset(), SXTW)); in CheckCharacters()
314 Operand(capture_start_offset, SXTW)); in CheckNotBackReferenceIgnoreCase()
317 Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
320 Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
324 Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
361 Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
364 __ Cmp(current_input_offset().X(), Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
386 __ Add(x0, input_end(), Operand(capture_start_offset, SXTW)); in CheckNotBackReferenceIgnoreCase()
390 __ Add(x1, input_end(), Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
392 __ Sub(x1, x1, Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 47 SXTW, enumerator
66 case AArch64_AM::SXTW: return "sxtw"; in getShiftExtendName()
133 case 6: return AArch64_AM::SXTW; in getExtendType()
160 case AArch64_AM::SXTW: return 6; break; in getExtendEncoding()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 47 SXTW, enumerator
66 case AArch64_AM::SXTW: return "sxtw"; in getShiftExtendName()
133 case 6: return AArch64_AM::SXTW; in getExtendType()
160 case AArch64_AM::SXTW: return 6; break; in getExtendEncoding()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 1070 // SXTW(8|16|32|64)
1071 def ZPR#RegWidth#AsmOpndExtSXTW8Only : ZPRExtendAsmOperand<"SXTW", RegWidth, 8, 0b1>;
1072 def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;
1073 def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;
1074 def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;
1075 def ZPR#RegWidth#AsmOpndExtSXTW64 : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>;
1077 …def ZPR#RegWidth#ExtSXTW8Only : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8, "On…
1078 def ZPR#RegWidth#ExtSXTW8 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>;
1079 def ZPR#RegWidth#ExtSXTW16 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>;
1080 def ZPR#RegWidth#ExtSXTW32 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>;
[all …]
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| D | AArch64FastISel.cpp | 723 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
807 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
865 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
1036 if (Addr.getExtendType() == AArch64_AM::SXTW || in simplifyAddress()
1052 else if (Addr.getExtendType() == AArch64_AM::SXTW) in simplifyAddress()
1113 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW || in addLoadStoreOperands()
1825 Addr.getExtendType() == AArch64_AM::SXTW) in emitLoad()
2114 Addr.getExtendType() == AArch64_AM::SXTW) in emitStore()
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| D | AArch64ISelDAGToDAG.cpp | 431 return AArch64_AM::SXTW; in getExtendTypeForNode()
848 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectExtendedSHL()
917 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectAddrModeWRO()
929 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectAddrModeWRO()
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| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 201 COMPARE_MACRO(Mov(x16, Operand(x17, SXTW, 3)), "sbfiz x16, x17, #3, #32"); in TEST()
440 COMPARE(add(x24, x25, Operand(x26, SXTW, 1)), "add x24, x25, w26, sxtw #1"); in TEST()
466 COMPARE(sub(x24, x25, Operand(x26, SXTW, 1)), "sub x24, x25, w26, sxtw #1"); in TEST()
1110 COMPARE(ldr(w12, MemOperand(x13, w14, SXTW)), "ldr w12, [x13, w14, sxtw]"); in TEST()
1111 COMPARE(ldr(w15, MemOperand(x16, w17, SXTW, 2)), in TEST()
1120 COMPARE(ldr(x12, MemOperand(x13, w14, SXTW)), "ldr x12, [x13, w14, sxtw]"); in TEST()
1121 COMPARE(ldr(x15, MemOperand(x16, w17, SXTW, 3)), in TEST()
1131 COMPARE(str(w12, MemOperand(x13, w14, SXTW)), "str w12, [x13, w14, sxtw]"); in TEST()
1132 COMPARE(str(w15, MemOperand(x16, w17, SXTW, 2)), in TEST()
1141 COMPARE(str(x12, MemOperand(x13, w14, SXTW)), "str x12, [x13, w14, sxtw]"); in TEST()
[all …]
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| D | test-api-aarch64.cc | 362 VIXL_CHECK(!Operand(w16, SXTW).IsPlainRegister()); in TEST()
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| D | test-cpu-features-aarch64.cc | 235 TEST_NONE(cmn_2, cmn(x0, Operand(w1, SXTW, 3)))
299 TEST_NONE(ldrb_4, ldrb(w0, MemOperand(x1, w2, SXTW, 0)))
316 TEST_NONE(ldrsb_10, ldrsb(x0, MemOperand(x1, w2, SXTW, 0)))
326 TEST_NONE(ldrsh_8, ldrsh(x0, MemOperand(x1, w2, SXTW, 0)))
332 TEST_NONE(ldrsw_4, ldrsw(x0, MemOperand(x1, w2, SXTW, 0)))
342 TEST_NONE(ldr_8, ldr(w0, MemOperand(x1, w2, SXTW, 0)))
404 TEST_NONE(prfm_2, prfm(PLDL1KEEP, MemOperand(x0, w1, SXTW, 0)))
455 TEST_NONE(strb_4, strb(w0, MemOperand(x1, w2, SXTW, 0)))
468 TEST_NONE(str_6, str(w0, MemOperand(x1, w2, SXTW, 2)))
489 TEST_NONE(sub_0, sub(w0, w1, Operand(w2, SXTW, 0)))
[all …]
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| D | test-assembler-aarch64.cc | 496 __ Mvn(x15, Operand(w2, SXTW, 4)); in TEST()
732 __ Mov(x30, Operand(x12, SXTW, 1)); in TEST()
807 __ Orr(x12, x0, Operand(x1, SXTW, 2)); in TEST()
901 __ Orn(x12, x0, Operand(x1, SXTW, 2)); in TEST()
968 __ And(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1106 __ Bic(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1230 __ Eor(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1297 __ Eon(x12, x0, Operand(x1, SXTW, 2)); in TEST()
3411 __ Ldr(w3, MemOperand(x18, x27, SXTW)); in TEST()
3412 __ Ldr(w4, MemOperand(x18, x28, SXTW, 2)); in TEST()
[all …]
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.cc | 407 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
468 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
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| D | constants-aarch64.h | 297 SXTW = 6, enumerator
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| D | simulator-aarch64.cc | 443 case SXTW: in ExtendValue()
1405 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | disasm-aarch64.cc | 5639 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 366 SXTW, enumerator
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| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 429 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
479 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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| D | constants-arm64.h | 381 SXTW = 6, enumerator
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| D | simulator-arm64.cc | 879 case SXTW: in ExtendValue()
1717 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | disasm-arm64.cc | 3967 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 407 SXTW, enumerator
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 676 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
760 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
818 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
990 if (Addr.getExtendType() == AArch64_AM::SXTW || in simplifyAddress()
1006 else if (Addr.getExtendType() == AArch64_AM::SXTW) in simplifyAddress()
1067 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW || in addLoadStoreOperands()
1771 Addr.getExtendType() == AArch64_AM::SXTW) in emitLoad()
2038 Addr.getExtendType() == AArch64_AM::SXTW) in emitStore()
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| D | AArch64ISelDAGToDAG.cpp | 381 return AArch64_AM::SXTW; in getExtendTypeForNode()
791 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectExtendedSHL()
860 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectAddrModeWRO()
872 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectAddrModeWRO()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1087 ShiftExtendTy == AArch64_AM::SXTW) && in isSVEDataVectorRegWithShiftExtend()
1238 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1274 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1731 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
1743 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
2672 .Case("sxtw", AArch64_AM::SXTW) in tryParseOptionalShiftExtend()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 990 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1025 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1577 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
1589 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
2395 .Case("sxtw", AArch64_AM::SXTW) in tryParseOptionalShiftExtend()
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 131 return Operand(InputRegister32(index), SXTW); in InputOperand2_32()
161 return Operand(InputRegister64(index), SXTW); in InputOperand2_64()
|