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Searched refs:SetCC (Results 1 – 25 of 49) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Dsetcc-takes-i32.ll4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dsetcc-takes-i32.ll4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
/external/v8/src/arm/
Dcodegen-arm.cc80 __ sub(chars, chars, Operand(64), SetCC); in CreateMemCopyUint8Function()
139 __ bic(temp1, chars, Operand(0x3), SetCC); in CreateMemCopyUint8Function()
148 __ bic(temp2, chars, Operand(0x3), SetCC); in CreateMemCopyUint8Function()
160 __ mov(chars, Operand(chars, LSL, 31), SetCC); in CreateMemCopyUint8Function()
245 __ mov(chars, Operand(chars, LSL, 31), SetCC); // bit0 => ne, bit1 => cs in CreateMemCopyUint16Uint8Function()
Dconstants-arm.h223 SetCC = 1 << 20, // Set condition code. enumerator
Dmacro-assembler-arm.cc1041 rsb(scratch, shift, Operand(32), SetCC); in LslPair()
1089 rsb(scratch, shift, Operand(32), SetCC); in LsrPair()
1138 rsb(scratch, shift, Operand(32), SetCC); in AsrPair()
1933 SmiUntag(dst, src, SetCC); in UntagAndJumpIfSmi()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrCMovSetCC.td1 //===- X86InstrCMovSetCC.td - Conditional Move and SetCC ---*- tablegen -*-===//
16 // SetCC instructions.
76 // SetCC instructions.
/external/v8/src/builtins/arm/
Dbuiltins-arm.cc148 __ sub(r5, r5, Operand(1), SetCC); in Generate_JSBuiltinsConstructStubHelper()
277 __ sub(r5, r5, Operand(1), SetCC); in Generate_JSConstructStubGeneric()
897 __ sub(r4, r4, Operand(kPointerSize), SetCC); in Generate_InterpreterEntryTrampoline()
1381 __ sub(r4, r0, Operand(1), SetCC); in Generate_FunctionPrototypeApply()
1383 __ sub(r4, r4, Operand(1), SetCC, ge); in Generate_FunctionPrototypeApply()
1477 __ sub(r4, r0, Operand(1), SetCC); in Generate_ReflectApply()
1479 __ sub(r4, r4, Operand(1), SetCC, ge); in Generate_ReflectApply()
1481 __ sub(r4, r4, Operand(1), SetCC, ge); in Generate_ReflectApply()
1519 __ sub(r4, r0, Operand(1), SetCC); in Generate_ReflectConstruct()
1522 __ sub(r4, r4, Operand(1), SetCC, ge); in Generate_ReflectConstruct()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/ConstProp/
D2002-09-03-SetCC-Bools.ll1 ; SetCC on boolean values was not implemented!
/external/swiftshader/third_party/LLVM/test/Transforms/ConstProp/
D2002-09-03-SetCC-Bools.ll1 ; SetCC on boolean values was not implemented!
/external/llvm/test/Transforms/ConstProp/
D2002-09-03-SetCC-Bools.ll1 ; SetCC on boolean values was not implemented!
/external/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
82 // SetCC instructions.
DX86ISelLowering.cpp15613 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC() local
15617 SetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, SetCC, in LowerSETCC()
15619 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); in LowerSETCC()
15621 return SetCC; in LowerSETCC()
15642 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC() local
15645 SetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, SetCC, in LowerSETCC()
15647 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); in LowerSETCC()
15649 return SetCC; in LowerSETCC()
15665 SDValue SetCC = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in LowerSETCCE() local
15668 SetCC = DAG.getNode(ISD::AssertZext, DL, MVT::i8, SetCC, in LowerSETCCE()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1307 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1310 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1313 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
80 // SetCC instructions.
DX86ISelLowering.cpp20893 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
20896 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
20898 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
20902 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
20904 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
20908 SetCC = getSETCC(X86::COND_A, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
20911 SetCC = getSETCC(X86::COND_A, InvComi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
20915 SetCC = getSETCC(X86::COND_AE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
20918 SetCC = getSETCC(X86::COND_AE, InvComi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
20923 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
[all …]
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp582 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
584 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
585 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
609 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
612 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
613 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); in performSELECTCombine()
615 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
638 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
645 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
646 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp677 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
679 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
680 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
704 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
707 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
708 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); in performSELECTCombine()
710 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
733 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
740 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
741 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
[all …]
/external/v8/src/regexp/arm/
Dregexp-macro-assembler-arm.cc214 __ sub(r1, r1, r0, SetCC); // Length of capture. in CheckNotBackReferenceIgnoreCase()
357 __ sub(r1, r1, r0, SetCC); // Length to check. in CheckNotBackReference()
654 __ sub(r0, sp, r0, SetCC); in GetCode()
717 __ sub(r2, r2, Operand(1), SetCC); in GetCode()
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc39 return SetCC; in OutputSBit()
427 SBit::SetCC); \
1204 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
1208 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
1212 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
1216 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
1224 SBit::SetCC); in AssembleArchInstruction()
1235 SBit::SetCC); in AssembleArchInstruction()
1298 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
1349 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
DO3-pipeline.ll89 ; CHECK-NEXT: X86 Fixup SetCC
/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
Dselect.ll22 ; A SetCC whose result is used should produce instructions to
/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1261 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1264 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1267 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Dselect.ll22 ; A SetCC whose result is used should produce instructions to
/external/llvm/test/CodeGen/Generic/
Dselect.ll22 ; A SetCC whose result is used should produce instructions to
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1368 SDNode *SetCC = nullptr; in LowerBRCOND() local
1372 SetCC = Intr; in LowerBRCOND()
1373 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
1386 assert(!SetCC || in LowerBRCOND()
1387 (SetCC->getConstantOperandVal(1) == 1 && in LowerBRCOND()
1388 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == in LowerBRCOND()

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