| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 2581 int64_t ShiftAmount = Const->getValue(); in lowerInt64Arithmetic() local
2582 if (ShiftAmount == 1) { in lowerInt64Arithmetic()
2588 } else if (ShiftAmount < INT32_BITS) { in lowerInt64Arithmetic()
2590 _srl(T1, Src0LoR, INT32_BITS - ShiftAmount); in lowerInt64Arithmetic()
2591 _sll(T2, Src0HiR, ShiftAmount); in lowerInt64Arithmetic()
2593 _sll(T_Lo, Src0LoR, ShiftAmount); in lowerInt64Arithmetic()
2594 } else if (ShiftAmount == INT32_BITS) { in lowerInt64Arithmetic()
2597 } else if (ShiftAmount > INT32_BITS && ShiftAmount < 64) { in lowerInt64Arithmetic()
2598 _sll(T_Hi, Src0LoR, ShiftAmount - INT32_BITS); in lowerInt64Arithmetic()
2640 int64_t ShiftAmount = Const->getValue(); in lowerInt64Arithmetic() local
[all …]
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| D | IceTargetLoweringX86BaseImpl.h | 1720 uint32_t ShiftAmount = ConstantShiftAmount->getValue();
1721 if (ShiftAmount > 32) {
1722 Constant *ReducedShift = Ctx->getConstantInt32(ShiftAmount - 32);
1765 } else if (ShiftAmount == 32) {
2840 SizeT ShiftAmount =
2843 Constant *ShiftConstant = Ctx->getConstantInt8(ShiftAmount);
2878 Constant *ShiftAmount = Ctx->getConstantInt32(DestBits - 1);
2887 _shl(T, ShiftAmount);
2888 _sar(T, ShiftAmount);
5563 uint32_t ShiftAmount = Const->getValue();
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.h | 49 unsigned ShiftAmount) const;
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| D | MipsTargetStreamer.h | 140 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
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| D | MipsSEISelDAGToDAG.cpp | 336 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
339 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
350 if (OffsetToAlignment(CN->getZExtValue(), 1ull << ShiftAmount) != 0) in selectAddrFrameIndexOffset()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 1170 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); in emitLoadImm() local
1171 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); in emitLoadImm()
1178 .addImm(ShiftAmount)); in emitLoadImm()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 200 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
202 if (ShiftAmount >= 32) { in emitDSLL()
203 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
207 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| D | MipsMCCodeEmitter.h | 185 template <unsigned ShiftAmount = 0>
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| D | MipsMCCodeEmitter.cpp | 780 template <unsigned ShiftAmount>
790 OffBits >>= ShiftAmount; in getMemEncoding()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 232 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
234 if (ShiftAmount >= 32) { in emitDSLL()
235 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
239 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| D | MipsMCCodeEmitter.h | 189 template <unsigned ShiftAmount = 0>
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| D | MipsMCCodeEmitter.cpp | 754 template <unsigned ShiftAmount>
764 OffBits >>= ShiftAmount; in getMemEncoding()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 199 unsigned ShiftAmount; member
351 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
704 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
742 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImmNeg()
1271 unsigned ShiftAmt = isShiftedImm() ? ShiftedImm.ShiftAmount : 0; in addAddSubImmNegOperands()
1667 unsigned ShiftAmount, in CreateShiftedImm() argument
1672 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2274 uint64_t ShiftAmount = 0; in tryParseAddSubImm() local
2280 ShiftAmount = 12; in tryParseAddSubImm()
2284 Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, S, E, in tryParseAddSubImm()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 346 unsigned ShiftAmount; member
493 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
769 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1795 unsigned ShiftAmount = 0, in CreateReg() argument
1803 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
1814 unsigned ShiftAmount = 0, in CreateVectorReg() argument
1819 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
1859 unsigned ShiftAmount, in CreateShiftedImm() argument
1864 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2565 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseImmWithOptionalShift() local
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 615 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
622 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
626 ShiftAmount -= 1; in LowerShifts()
629 while (ShiftAmount--) in LowerShifts()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 736 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
743 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
747 ShiftAmount -= 1; in LowerShifts()
750 while (ShiftAmount--) in LowerShifts()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 91 unsigned &ShiftAmount);
2451 const MCExpr *ShiftAmount; in parsePKHImm() local
2453 if (getParser().ParseExpression(ShiftAmount)) { in parsePKHImm()
2457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
2529 const MCExpr *ShiftAmount; in parseShifterImm() local
2531 if (getParser().ParseExpression(ShiftAmount)) { in parseShifterImm()
2535 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
2589 const MCExpr *ShiftAmount; in parseRotImm() local
2591 if (getParser().ParseExpression(ShiftAmount)) { in parseRotImm()
2595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
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| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2357 unsigned ShiftAmount = CI2->getValue().countLeadingOnes() - 1; in SimplifyICmpInst() local
2358 Lower = CI2->getValue().shl(ShiftAmount); in SimplifyICmpInst()
2362 unsigned ShiftAmount = CI2->getValue().countLeadingZeros() - 1; in SimplifyICmpInst() local
2364 Upper = CI2->getValue().shl(ShiftAmount) + 1; in SimplifyICmpInst()
2373 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2375 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2376 Lower = CI2->getValue().lshr(ShiftAmount); in SimplifyICmpInst()
2387 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2389 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2393 Upper = CI2->getValue().ashr(ShiftAmount) + 1; in SimplifyICmpInst()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 827 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
829 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
830 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
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| D | LegalizeDAG.cpp | 1467 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN() local
1469 if (ShiftAmount > 0) { in ExpandFCOPYSIGN()
1470 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1472 } else if (ShiftAmount < 0) { in ExpandFCOPYSIGN()
1473 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1479 if (ShiftAmount > 0) { in ExpandFCOPYSIGN()
1480 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, MagVT); in ExpandFCOPYSIGN()
1482 } else if (ShiftAmount < 0) { in ExpandFCOPYSIGN()
1483 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, MagVT); in ExpandFCOPYSIGN()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 121 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2508 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
2510 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
2514 Upper = C->ashr(ShiftAmount) + 1; in setLimitsForBinOp()
2517 Lower = C->ashr(ShiftAmount); in setLimitsForBinOp()
2529 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
2531 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
2532 Lower = C->lshr(ShiftAmount); in setLimitsForBinOp()
2546 unsigned ShiftAmount = C->countLeadingOnes() - 1; in setLimitsForBinOp() local
2547 Lower = C->shl(ShiftAmount); in setLimitsForBinOp()
2551 unsigned ShiftAmount = C->countLeadingZeros() - 1; in setLimitsForBinOp() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 956 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
963 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
967 ShiftAmount -= 1; in LowerShifts()
970 while (ShiftAmount--) in LowerShifts()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 876 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
878 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
879 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
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| D | TargetLowering.cpp | 3698 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
3700 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) { in expandMUL_LOHI()
3706 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy); in expandMUL_LOHI()
3942 SDValue ShiftAmount = in scalarizeVectorStore() local
3945 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); in scalarizeVectorStore()
4120 SDValue ShiftAmount = in expandUnalignedLoad() local
4123 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in expandUnalignedLoad()
4237 SDValue ShiftAmount = in expandUnalignedStore() local
4241 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in expandUnalignedStore()
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