/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonMCDuplexInfo.cpp | 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local 317 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 319 if (HexagonMCInstrInfo::isIntReg(Src1Reg) && in getDuplexCandidateGroup() 321 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { in getDuplexCandidateGroup() 325 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup() 333 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 335 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup() 352 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 354 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup() 362 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() [all …]
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D | HexagonMCCompound.cpp | 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local 101 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup() 104 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup() 146 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup() 148 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup() 160 Src1Reg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup() 161 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg) in getCompoundCandidateGroup()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonMCDuplexInfo.cpp | 186 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local 319 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 321 if (HexagonMCInstrInfo::isIntReg(Src1Reg) && in getDuplexCandidateGroup() 323 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { in getDuplexCandidateGroup() 327 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup() 335 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 337 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup() 354 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 356 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup() 364 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() [all …]
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D | HexagonMCCompound.cpp | 82 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local 99 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup() 102 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup() 144 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup() 146 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup() 158 Src1Reg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup() 159 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg) in getCompoundCandidateGroup()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfo.cpp | 1139 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local 1141 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg); in expandPostRAPseudo() 1142 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg); in expandPostRAPseudo() 1163 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local 1166 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg); in expandPostRAPseudo() 1167 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg); in expandPostRAPseudo() 1193 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local 1206 .addReg(Src1Reg, Src1RegIsKill) in expandPostRAPseudo() 3304 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local 3319 Src1Reg = MI->getOperand(1).getReg(); in getCompoundCandidateGroup() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfo.cpp | 1167 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local 1169 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo() 1170 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo() 1191 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local 1194 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo() 1195 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo() 3238 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local 3253 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup() 3257 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg)) in getCompoundCandidateGroup() 3290 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 212 unsigned Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local 226 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 278 unsigned Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local 294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
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/external/llvm/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 278 unsigned Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local 294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
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/external/llvm/lib/Target/Mips/ |
D | MipsFastISel.cpp | 994 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local 998 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect() 1016 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect() 1685 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectDivRem() local 1686 if (!Src0Reg || !Src1Reg) in selectDivRem() 1689 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem() 1690 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsFastISel.cpp | 1032 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local 1036 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect() 1054 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect() 1911 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectDivRem() local 1912 if (!Src0Reg || !Src1Reg) in selectDivRem() 1915 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem() 1916 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 2647 unsigned Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local 2648 if (!Src1Reg) in optimizeSelect() 2658 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect() 2661 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect() 2777 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local 2783 if (!Src1Reg || !Src2Reg) in selectSelect() 2787 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() 2791 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() 4573 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local 4574 if (!Src1Reg) in selectRem() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 2558 unsigned Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local 2559 if (!Src1Reg) in optimizeSelect() 2569 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect() 2572 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect() 2688 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local 2694 if (!Src1Reg || !Src2Reg) in selectSelect() 2698 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() 2702 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() 4487 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local 4488 if (!Src1Reg) in selectRem() [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | R600InstrInfo.h | 270 unsigned Src1Reg = 0) const;
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D | R600InstrInfo.cpp | 1265 unsigned Src1Reg) const { in buildDefaultInstruction() 1269 if (Src1Reg) { in buildDefaultInstruction() 1283 if (Src1Reg) { in buildDefaultInstruction() 1284 MIB.addReg(Src1Reg) // $src1 in buildDefaultInstruction()
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D | SIInstrInfo.cpp | 1265 unsigned Src1Reg = Src1->getReg(); in FoldImmediate() local 1267 Src0->setReg(Src1Reg); in FoldImmediate()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | R600InstrInfo.h | 272 unsigned Src1Reg = 0) const;
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D | R600InstrInfo.cpp | 1244 unsigned Src1Reg) const { in buildDefaultInstruction() 1248 if (Src1Reg) { in buildDefaultInstruction() 1262 if (Src1Reg) { in buildDefaultInstruction() 1263 MIB.addReg(Src1Reg) // $src1 in buildDefaultInstruction()
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D | SIInstrInfo.cpp | 2042 unsigned Src1Reg = Src1->getReg(); in FoldImmediate() local 2044 Src0->setReg(Src1Reg); in FoldImmediate()
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