| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 872 unsigned SrcReg1 = getRegForValue(SrcValue1); in PPCEmitCmp() local
873 if (SrcReg1 == 0) in PPCEmitCmp()
885 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
887 SrcReg1 = ExtReg; in PPCEmitCmp()
899 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
902 .addReg(SrcReg1).addImm(Imm); in PPCEmitCmp()
1204 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1205 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1218 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1222 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 921 unsigned SrcReg1 = getRegForValue(SrcValue1); in PPCEmitCmp() local
922 if (SrcReg1 == 0) in PPCEmitCmp()
934 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
936 SrcReg1 = ExtReg; in PPCEmitCmp()
948 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
951 .addReg(SrcReg1).addImm(Imm); in PPCEmitCmp()
1291 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1292 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1305 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1309 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
[all …]
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| D | PPCInstrInfo.cpp | 3379 unsigned SrcReg1 = MI.getOperand(1).getReg(); in isSignOrZeroExtended() local
3382 if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) || in isSignOrZeroExtended()
3386 const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1); in isSignOrZeroExtended()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SIMDInstrOpt.cpp | 433 unsigned SrcReg1 = MI.getOperand(2).getReg(); in optimizeVectElement() local
453 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
457 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg1, LaneNumber, &DupDest)) { in optimizeVectElement()
460 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
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| D | AArch64InstrInfo.cpp | 4047 unsigned SrcReg1 = MUL->getOperand(2).getReg(); in genFusedMultiply() local
4065 if (TargetRegisterInfo::isVirtualRegister(SrcReg1)) in genFusedMultiply()
4066 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
4074 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
4080 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
4086 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply()
4124 unsigned SrcReg1 = MUL->getOperand(2).getReg(); in genMaddR() local
4131 if (TargetRegisterInfo::isVirtualRegister(SrcReg1)) in genMaddR()
4132 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
4139 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMaddR()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1422 unsigned SrcReg1 = getRegForValue(Src1Value); in ARMEmitCmp() local
1423 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1433 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1434 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1442 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1446 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1450 .addReg(SrcReg1); in ARMEmitCmp()
1758 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1759 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1767 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1435 unsigned SrcReg1 = getRegForValue(Src1Value); in ARMEmitCmp() local
1436 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1446 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1447 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1455 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1459 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1463 .addReg(SrcReg1); in ARMEmitCmp()
1782 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1783 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1791 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3292 unsigned SrcReg1 = MUL->getOperand(2).getReg(); in genFusedMultiply() local
3301 if (TargetRegisterInfo::isVirtualRegister(SrcReg1)) in genFusedMultiply()
3302 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
3310 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
3316 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
3322 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply()
3356 unsigned SrcReg1 = MUL->getOperand(2).getReg(); in genMaddR() local
3363 if (TargetRegisterInfo::isVirtualRegister(SrcReg1)) in genMaddR()
3364 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
3371 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMaddR()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 63 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) in emit2() argument
74 fpi->U.I.SrcReg[1] = SrcReg1; in emit2()
82 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, in emit3() argument
94 fpi->U.I.SrcReg[1] = SrcReg1; in emit3()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 570 unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy); in narrowScalar() local
574 SrcsReg1.push_back(SrcReg1); in narrowScalar()
|