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Searched refs:SrcReg2 (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp180 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
188 SrcReg2 = 0; in analyzeCompare()
194 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
208 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
213 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
214 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
286 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
306 if (SrcReg2 != 0) in optimizeCompareInstr()
332 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
384 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
DLanaiInstrInfo.h95 unsigned &SrcReg2, int &CmpMask,
102 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp179 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
187 SrcReg2 = 0; in analyzeCompare()
193 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
207 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
212 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
213 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
285 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
305 if (SrcReg2 != 0) in optimizeCompareInstr()
331 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
383 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
DLanaiInstrInfo.h97 unsigned &SrcReg2, int &CmpMask,
104 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp407 unsigned SrcReg2 = in fuseCompareOperations() local
412 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareOperations()
459 if (SrcReg2) in fuseCompareOperations()
460 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareOperations()
DSystemZInstrInfo.h172 unsigned &SrcReg2, int &Mask, int &Value) const override;
174 unsigned SrcReg2, int Mask, int Value,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp528 unsigned SrcReg2 = in fuseCompareOperations() local
533 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareOperations()
585 if (SrcReg2) in fuseCompareOperations()
586 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareOperations()
DSystemZInstrInfo.h210 unsigned &SrcReg2, int &Mask, int &Value) const override;
212 unsigned SrcReg2, int Mask, int Value,
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h250 unsigned &SrcReg2, int &Mask, int &Value) const override;
253 unsigned SrcReg2, int Mask, int Value,
DPPCFastISel.cpp876 unsigned SrcReg2 = 0; in PPCEmitCmp() local
878 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
879 if (SrcReg2 == 0) in PPCEmitCmp()
891 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
893 SrcReg2 = ExtReg; in PPCEmitCmp()
899 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1262 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1263 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1267 std::swap(SrcReg1, SrcReg2); in SelectBinaryIntOp()
1270 .addReg(SrcReg1).addReg(SrcReg2); in SelectBinaryIntOp()
DPPCInstrInfo.cpp1500 unsigned &SrcReg2, int &Mask, in analyzeCompare() argument
1511 SrcReg2 = 0; in analyzeCompare()
1522 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1528 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr() argument
1635 if (SrcReg2 != 0) in optimizeCompareInstr()
1672 Instr.getOperand(2).getReg() == SrcReg2) || in optimizeCompareInstr()
1673 (Instr.getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
1719 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h166 unsigned &SrcReg2, int &CmpMask,
171 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h315 unsigned &SrcReg2, int &Mask, int &Value) const override;
318 unsigned SrcReg2, int Mask, int Value,
DPPCFastISel.cpp925 unsigned SrcReg2 = 0; in PPCEmitCmp() local
927 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
928 if (SrcReg2 == 0) in PPCEmitCmp()
940 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
942 SrcReg2 = ExtReg; in PPCEmitCmp()
948 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1349 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1350 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1354 std::swap(SrcReg1, SrcReg2); in SelectBinaryIntOp()
1357 .addReg(SrcReg1).addReg(SrcReg2); in SelectBinaryIntOp()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h196 unsigned &SrcReg2, int &CmpMask,
201 unsigned SrcReg2, int CmpMask, int CmpValue,
DAArch64SIMDInstrOpt.cpp439 unsigned SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
445 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
448 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1425 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1427 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1428 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1436 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1437 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1444 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1446 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
DARMBaseInstrInfo.h254 unsigned &SrcReg2, int &CmpMask,
262 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMFastISel.cpp1438 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1440 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1441 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1449 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1450 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1457 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1459 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1787 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1788 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1792 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
DARMBaseInstrInfo.h285 unsigned &SrcReg2, int &CmpMask,
293 unsigned SrcReg2, int CmpMask, int CmpValue,
DARMBaseInstrInfo.cpp2517 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
2525 SrcReg2 = 0; in analyzeCompare()
2532 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
2539 SrcReg2 = 0; in analyzeCompare()
2606 unsigned SrcReg, unsigned SrcReg2, in isRedundantFlagInstr() argument
2613 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
2614 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
2631 OI->getOperand(1).getReg() == SrcReg2) in isRedundantFlagInstr()
2701 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
2740 if (SrcReg2 != 0) in optimizeCompareInstr()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrInfo.h504 unsigned &SrcReg2, int &CmpMask,
511 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp565 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
567 if (!TII->analyzeCompare(*MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
569 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) in optimizeCmpInstr()
573 if (TII->optimizeCompareInstr(*MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrInfo.h519 unsigned &SrcReg2, int &CmpMask,
526 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp610 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
614 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) in optimizeCmpInstr()
618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()

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