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Searched refs:SrcVec (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIcePhiLoweringImpl.h65 auto *SrcVec = llvm::cast<VariableVecOn32>(Src); in prelowerPhis32Bit() local
66 PhiElem->addArgument(SrcVec->getContainers()[Idx], Label); in prelowerPhis32Bit()
DIceTargetLoweringMIPS32.cpp5499 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); in lowerRet() local
5501 legalizeToReg(SrcVec->getContainers()[0], RegMIPS32::Reg_V0); in lowerRet()
5503 legalizeToReg(SrcVec->getContainers()[1], RegMIPS32::Reg_V1); in lowerRet()
5505 legalizeToReg(SrcVec->getContainers()[2], RegMIPS32::Reg_A0); in lowerRet()
5507 legalizeToReg(SrcVec->getContainers()[3], RegMIPS32::Reg_A1); in lowerRet()
5515 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); in lowerRet() local
5519 for (SizeT i = 0; i < SrcVec->ContainersPerVector; ++i) { in lowerRet()
5523 Variable *Var = legalizeToReg(SrcVec->getContainers()[i]); in lowerRet()
/external/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp187 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
199 .addReg(SrcVec) in RebuildVector()
212 SrcVec = DstReg; in RebuildVector()
215 BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg).addReg(SrcVec); in RebuildVector()
DSILowerControlFlow.cpp633 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in indirectSrc() local
637 std::tie(Reg, Offset) = computeIndirectRegAndOffset(SrcVec->getReg(), Offset); in indirectSrc()
643 .addReg(Reg, getUndefRegState(SrcVec->isUndef())); in indirectSrc()
650 .addReg(Reg, getUndefRegState(SrcVec->isUndef())) in indirectSrc()
651 .addReg(SrcVec->getReg(), RegState::Implicit); in indirectSrc()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp211 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
223 .addReg(SrcVec) in RebuildVector()
234 SrcVec = DstReg; in RebuildVector()
237 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
DSIISelLowering.cpp3138 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
3142 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst()
3149 SrcVec->getReg(), in emitIndirectDst()
3160 .add(*SrcVec) in emitIndirectDst()
3174 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst in emitIndirectDst()
3177 .addReg(SrcVec->getReg(), RegState::Implicit) in emitIndirectDst()
3186 .addReg(SrcVec->getReg()) in emitIndirectDst()
3202 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, in emitIndirectDst()
/external/swiftshader/third_party/LLVM/lib/VMCore/
DVerifier.cpp946 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
949 Assert1(SrcVec == DstVec, in visitUIToFPInst()
956 if (SrcVec && DstVec) in visitUIToFPInst()
969 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
972 Assert1(SrcVec == DstVec, in visitSIToFPInst()
979 if (SrcVec && DstVec) in visitSIToFPInst()
992 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
995 Assert1(SrcVec == DstVec, in visitFPToUIInst()
1002 if (SrcVec && DstVec) in visitFPToUIInst()
1015 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/external/llvm/lib/IR/
DVerifier.cpp2318 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2321 Assert(SrcVec == DstVec, in visitUIToFPInst()
2328 if (SrcVec && DstVec) in visitUIToFPInst()
2341 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2344 Assert(SrcVec == DstVec, in visitSIToFPInst()
2351 if (SrcVec && DstVec) in visitSIToFPInst()
2364 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2367 Assert(SrcVec == DstVec, in visitFPToUIInst()
2374 if (SrcVec && DstVec) in visitFPToUIInst()
2387 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/
DVerifier.cpp2513 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2516 Assert(SrcVec == DstVec, in visitUIToFPInst()
2523 if (SrcVec && DstVec) in visitUIToFPInst()
2536 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2539 Assert(SrcVec == DstVec, in visitSIToFPInst()
2546 if (SrcVec && DstVec) in visitSIToFPInst()
2559 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2562 Assert(SrcVec == DstVec, in visitFPToUIInst()
2569 if (SrcVec && DstVec) in visitFPToUIInst()
2582 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1500 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1512 SrcVec = Src; in executeBitCastInst()
1518 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1539 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1544 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1547 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
/external/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1501 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1513 SrcVec = Src; in executeBitCastInst()
1519 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1540 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1545 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1548 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp6221 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
6222 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask()
6230 Ops.push_back(SrcVec); in getFauxShuffleMask()
8014 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute() argument
8031 if (SrcVec.getValueSizeInBits() != SizeInBits) { in createVariablePermute()
8032 if ((SrcVec.getValueSizeInBits() % SizeInBits) == 0) { in createVariablePermute()
8034 unsigned Scale = SrcVec.getValueSizeInBits() / SizeInBits; in createVariablePermute()
8040 createVariablePermute(VT, SrcVec, IndicesVec, DL, DAG, Subtarget), 0, in createVariablePermute()
8042 } else if (SrcVec.getValueSizeInBits() < SizeInBits) { in createVariablePermute()
8044 SrcVec = widenSubVector(VT, SrcVec, false, Subtarget, DAG, SDLoc(SrcVec)); in createVariablePermute()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp5686 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
5689 SrcVec = V2; in LowerVECTOR_SHUFFLE()
5701 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp6470 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
6473 SrcVec = V2; in LowerVECTOR_SHUFFLE()
6485 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp30149 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0, in combineToExtendVectorInReg() local
30151 SrcVec = ExtendVecSize(DL, SrcVec, 128); in combineToExtendVectorInReg()
30152 SrcVec = Opcode == ISD::SIGN_EXTEND in combineToExtendVectorInReg()
30153 ? DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT) in combineToExtendVectorInReg()
30154 : DAG.getZeroExtendVectorInReg(SrcVec, DL, SubVT); in combineToExtendVectorInReg()
30155 Opnds.push_back(SrcVec); in combineToExtendVectorInReg()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp10351 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
10355 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl)); in DAGCombineBuildVector()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp12144 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
12148 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl)); in DAGCombineBuildVector()