| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3649 SDValue StVal = MST->getValue(); in WidenVecOp_MSTORE() local
3654 StVal = GetWidenedVector(StVal); in WidenVecOp_MSTORE()
3657 EVT WideVT = StVal.getValueType(); in WidenVecOp_MSTORE()
3666 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE()
3668 StVal = GetWidenedVector(StVal); in WidenVecOp_MSTORE()
3673 StVal = ModifyToType(StVal, WideVT); in WidenVecOp_MSTORE()
3678 StVal.getValueType().getVectorNumElements() && in WidenVecOp_MSTORE()
3680 return DAG.getMaskedStore(MST->getChain(), dl, StVal, MST->getBasePtr(), in WidenVecOp_MSTORE()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9905 SDValue StVal = St.getValue(); in replaceZeroVectorStore() local
9906 EVT VT = StVal.getValueType(); in replaceZeroVectorStore()
9917 if (StVal.getOpcode() != ISD::BUILD_VECTOR) in replaceZeroVectorStore()
9923 if (!StVal.hasOneUse()) in replaceZeroVectorStore()
9935 SDValue EltVal = StVal.getOperand(I); in replaceZeroVectorStore()
9963 SDValue StVal = St.getValue(); in replaceSplatVectorStore() local
9964 EVT VT = StVal.getValueType(); in replaceSplatVectorStore()
9983 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
9988 SplatVal = StVal.getOperand(1); in replaceSplatVectorStore()
9989 else if (StVal.getOperand(1) != SplatVal) in replaceSplatVectorStore()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1499 SDValue StVal = OutVals[OIdx]; in LowerCall() local
1503 StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND in LowerCall()
1505 dl, MVT::i32, StVal); in LowerCall()
1509 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); in LowerCall()
1513 StoreOperands.push_back(StVal); in LowerCall()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 10071 SDValue &StVal = Ops[Ops.size()-2]; in CombineBaseUpdate() local
10072 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); in CombineBaseUpdate()
10244 SDValue StVal = St->getValue(); in PerformSTORECombine() local
10245 EVT VT = StVal.getValueType(); in PerformSTORECombine()
10271 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformSTORECombine()
10328 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
10329 StVal.getNode()->hasOneUse()) { in PerformSTORECombine()
10335 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ), in PerformSTORECombine()
10342 StVal.getNode()->getOperand(isBigEndian ? 0 : 1), in PerformSTORECombine()
10348 if (StVal.getValueType() == MVT::i64 && in PerformSTORECombine()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 6973 SDValue StVal = St->getValue(); in PerformSTORECombine() local
6977 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
6978 StVal.getNode()->hasOneUse() && !St->isVolatile()) { in PerformSTORECombine()
6983 StVal.getNode()->getOperand(0), BasePtr, in PerformSTORECombine()
6989 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), in PerformSTORECombine()
6995 if (StVal.getValueType() != MVT::i64 || in PerformSTORECombine()
6996 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in PerformSTORECombine()
7000 DebugLoc dl = StVal.getDebugLoc(); in PerformSTORECombine()
7001 SDValue IntVec = StVal.getOperand(0); in PerformSTORECombine()
7006 Vec, StVal.getOperand(1)); in PerformSTORECombine()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 11704 SDValue &StVal = Ops[Ops.size()-2]; in CombineBaseUpdate() local
11705 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); in CombineBaseUpdate()
11902 SDValue StVal = St->getValue(); in PerformSTORECombine() local
11903 EVT VT = StVal.getValueType(); in PerformSTORECombine()
11929 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformSTORECombine()
11986 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
11987 StVal.getNode()->hasOneUse()) { in PerformSTORECombine()
11993 St->getChain(), DL, StVal.getNode()->getOperand(isBigEndian ? 1 : 0), in PerformSTORECombine()
12000 StVal.getNode()->getOperand(isBigEndian ? 0 : 1), in PerformSTORECombine()
12006 if (StVal.getValueType() == MVT::i64 && in PerformSTORECombine()
[all …]
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1124 SDValue StVal = OutVals[OIdx]; in LowerCall() local
1126 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); in LowerCall()
1132 StVal, InFlag }; in LowerCall()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 8691 SDValue StVal = St->getValue(); in replaceSplatVectorStore() local
8692 EVT VT = StVal.getValueType(); in replaceSplatVectorStore()
8700 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
8707 SDValue SplatVal = StVal.getOperand(1); in replaceSplatVectorStore()
8712 SDValue NextInsertElt = StVal.getOperand(0); in replaceSplatVectorStore()
8717 StVal = NextInsertElt; in replaceSplatVectorStore()
8766 SDValue StVal = S->getValue(); in split16BStores() local
8767 EVT VT = StVal.getValueType(); in split16BStores()
8794 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in split16BStores()
8796 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in split16BStores()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3302 SDValue StVal = MST->getValue(); in WidenVecOp_MSTORE() local
3304 SDValue WideVal = GetWidenedVector(StVal); in WidenVecOp_MSTORE()
|