Home
last modified time | relevance | path

Searched refs:SubReg1 (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp215 unsigned SubReg1; in isProfitableToTransform() local
233 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
307 unsigned Src1 = 0, SubReg1; in transformInstruction() local
332 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
356 SubReg1 = 0; in transformInstruction()
372 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp208 unsigned SubReg1; in isProfitableToTransform() local
226 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
300 unsigned Src1 = 0, SubReg1; in transformInstruction() local
325 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
349 SubReg1 = 0; in transformInstruction()
365 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
DAArch64ISelLowering.cpp11177 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32); in createGPRPairNode() local
11178 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
11227 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; in ReplaceCMP_SWAP_128Results() local
11229 std::swap(SubReg1, SubReg2); in ReplaceCMP_SWAP_128Results()
11230 Results.push_back(DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelDAGToDAG.cpp1457 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); in PairSRegs() local
1458 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairSRegs()
1468 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); in PairDRegs() local
1469 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairDRegs()
1479 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); in PairQRegs() local
1480 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairQRegs()
1492 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); in QuadSRegs() local
1495 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadSRegs()
1507 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); in QuadDRegs() local
1510 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadDRegs()
[all …]
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1601 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1602 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1612 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1613 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1623 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1624 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1634 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1635 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1646 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode() local
1649 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
[all …]
DARMISelLowering.cpp7109 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
7110 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1516 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1517 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1527 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1528 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1538 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1539 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1549 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1550 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1561 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode() local
1564 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
[all …]
DARMISelLowering.cpp7974 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
7975 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetInstrInfo.cpp169 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
196 SubReg0 = SubReg1; in commuteInstructionImpl()
214 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp147 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
166 SubReg0 = SubReg1; in commuteInstructionImpl()
184 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp364 SDValue RC, SubReg0, SubReg1; in Select() local
372 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); in Select()
376 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
381 N->getOperand(1), SubReg1 }; in Select()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp526 SDValue RC, SubReg0, SubReg1; in Select() local
531 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); in Select()
535 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
540 N->getOperand(1), SubReg1 }; in Select()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp351 unsigned SubReg1 = MI.getOperand(1).getSubReg(); in commuteInstructionImpl() local
362 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); in commuteInstructionImpl()
394 MI.getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp387 unsigned SubReg1 = MI.getOperand(1).getSubReg(); in commuteInstructionImpl() local
398 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); in commuteInstructionImpl()
430 MI.getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()