| /external/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
225 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
226 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
336 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
337 if (SubRegIdx == 0) in computeMainRangesFixFlags()
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| D | RegisterPressure.cpp | 492 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
495 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
500 SubRegIdx = 0; in collectOperandLanes()
504 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
506 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
510 void pushRegLanes(unsigned Reg, unsigned SubRegIdx, in pushRegLanes() argument
513 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
514 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1192 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1193 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
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| D | StackMaps.cpp | 145 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
146 if (SubRegIdx) in parseOperand()
147 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
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| D | VirtRegMap.cpp | 340 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
341 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
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| D | MachineVerifier.cpp | 1224 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1225 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1226 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
1325 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1326 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1327 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
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| D | RegisterCoalescer.cpp | 214 MachineOperand &MO, unsigned SubRegIdx);
1217 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1218 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
348 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
349 if (SubRegIdx == 0) in computeMainRangesFixFlags()
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| D | RegisterPressure.cpp | 519 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
522 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
527 SubRegIdx = 0; in collectOperandLanes()
531 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
533 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
537 void pushRegLanes(unsigned Reg, unsigned SubRegIdx, in pushRegLanes() argument
540 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
541 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1213 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1214 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
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| D | VirtRegMap.cpp | 365 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
366 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
367 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
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| D | StackMaps.cpp | 160 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
161 if (SubRegIdx) in parseOperand()
162 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
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| D | MachineVerifier.cpp | 1488 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1489 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1490 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
1589 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1590 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1591 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
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| D | RegisterCoalescer.cpp | 234 MachineOperand &MO, unsigned SubRegIdx);
1500 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1501 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 655 unsigned SubRegIdx = (is32Bit ? in Select() local
660 CurDAG->getTargetConstant(SubRegIdx, in Select()
669 unsigned SubRegIdx = (is32Bit ? in Select() local
674 CurDAG->getTargetConstant(SubRegIdx, in Select()
715 unsigned SubRegIdx = (is32Bit ? in Select() local
720 CurDAG->getTargetConstant(SubRegIdx, MVT::i32)); in Select()
740 unsigned SubRegIdx = (is32Bit ? in Select() local
745 CurDAG->getTargetConstant(SubRegIdx, in Select()
753 unsigned SubRegIdx = (is32Bit ? in Select() local
758 CurDAG->getTargetConstant(SubRegIdx, in Select()
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 190 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
196 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
202 if (SubRegIdx == X86::sub_8bit) { in getSuperRegDestIfDead()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 181 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
187 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
195 if (SubRegIdx != X86::sub_8bit) in getSuperRegDestIfDead()
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| D | X86FlagsCopyLowering.cpp | 939 int SubRegIdx[] = {X86::NoSubRegister, X86::sub_8bit, X86::sub_16bit, in rewriteSetCarryExtended() local
962 .addImm(SubRegIdx[OrigRegSize]); in rewriteSetCarryExtended()
971 .addReg(Reg, 0, SubRegIdx[TargetRegSize]); in rewriteSetCarryExtended()
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| D | X86InstrAVX512.td | 101 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
3135 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3136 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))),
3145 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3146 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))),
3159 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3160 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
3169 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3170 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
3182 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
[all …]
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| D | X86ISelDAGToDAG.cpp | 850 unsigned SubRegIdx = N->getConstantOperandVal(2); in PostprocessISelDAG() local
851 if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) in PostprocessISelDAG()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 476 CodeGenSubRegIndex *SubRegIdx; in computeSecondarySubRegs() local
478 std::tie(SubRegIdx, SubReg) = SubRegQueue.front(); in computeSecondarySubRegs()
496 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
498 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs() local
499 if (SubRegIdx->ConcatenationOf.empty()) { in computeSecondarySubRegs()
500 Parts.push_back(SubRegIdx); in computeSecondarySubRegs()
502 for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf) in computeSecondarySubRegs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | InstructionSelectorImpl.h | 719 int64_t SubRegIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
722 0, SubRegIdx); in executeMatchTable()
726 << OpIdx << ", " << SubRegIdx << ")\n"); in executeMatchTable()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 1102 unsigned SubRegIdx = 0);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 156 unsigned SubRegIdx);
158 unsigned SubRegIdx);
1192 unsigned SubRegIdx) { in SelectLoad() argument
1206 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1219 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad() argument
1243 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 155 unsigned SubRegIdx);
157 unsigned SubRegIdx);
1135 unsigned SubRegIdx) { in SelectLoad() argument
1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1156 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad() argument
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 212 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue(); in getOperandRegClass() local
214 SubRegIdx); in getOperandRegClass()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 1582 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local
1587 SubRegIdx), 0); in ExtendToInt64()
2641 SDValue SubRegIdx = in addExtOrTrunc() local
2644 ImDef, NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
2651 SDValue SubRegIdx = in addExtOrTrunc() local
2654 NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
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