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Searched refs:SubRegIndices (Results 1 – 25 of 55) sorted by relevance

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/external/swiftshader/third_party/LLVM/utils/TableGen/
DRegisterInfoEmitter.cpp433 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); in runTargetHeader() local
434 if (!SubRegIndices.empty()) { in runTargetHeader()
436 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace"); in runTargetHeader()
441 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; in runTargetHeader()
442 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; in runTargetHeader()
692 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc() local
695 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { in runTargetDesc()
696 OS << SubRegIndices[i]->getName(); in runTargetDesc()
703 if (SubRegIndices.size() > NamedIndices) { in runTargetDesc()
705 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) { in runTargetDesc()
[all …]
DCodeGenRegisters.cpp518 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex"); in CodeGenRegBank()
519 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord()); in CodeGenRegBank()
520 NumNamedIndices = SubRegIndices.size(); in CodeGenRegBank()
602 SubRegIndices.push_back(Comp); in getCompositeSubRegIndex()
608 std::find(SubRegIndices.begin(), SubRegIndices.end(), idx); in getSubRegIndexNo()
609 assert(i != SubRegIndices.end() && "Not a SubRegIndex"); in getSubRegIndexNo()
610 return (i - SubRegIndices.begin()) + 1; in getSubRegIndexNo()
770 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { in computeInferredRegisterClasses()
771 Record *SubIdx = SubRegIndices[sri]; in computeInferredRegisterClasses()
DCodeGenRegisters.h226 std::vector<Record*> SubRegIndices; variable
259 const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; } in getSubRegIndices()
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp157 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums() local
158 if (!SubRegIndices.empty()) { in runEnums()
160 std::string Namespace = SubRegIndices.front().getNamespace(); in runEnums()
165 for (const auto &Idx : SubRegIndices) in runEnums()
650 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices() local
666 std::distance(SubRegIndices.begin(), SubRegIndices.end()); in emitComposeSubRegIndices()
667 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndices()
721 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask() local
726 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndexLaneMask()
769 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { in emitComposeSubRegIndexLaneMask()
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DCodeGenRegisters.cpp935 for (auto &Idx : SubRegIndices) in CodeGenRegBank()
1014 SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1); in createSubRegIndex()
1015 return &SubRegIndices.back(); in createSubRegIndex()
1022 SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1); in getSubRegIdx()
1023 Idx = &SubRegIndices.back(); in getSubRegIdx()
1171 for (auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1192 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1210 for (auto &Idx2 : SubRegIndices) { in computeSubRegLaneMasks()
1265 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1276 for (const auto &SubRegIndex : SubRegIndices) { in computeSubRegLaneMasks()
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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp171 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums() local
172 if (!SubRegIndices.empty()) { in runEnums()
174 std::string Namespace = SubRegIndices.front().getNamespace(); in runEnums()
179 for (const auto &Idx : SubRegIndices) in runEnums()
656 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices() local
672 std::distance(SubRegIndices.begin(), SubRegIndices.end()); in emitComposeSubRegIndices()
673 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndices()
727 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask() local
732 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndexLaneMask()
776 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { in emitComposeSubRegIndexLaneMask()
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DCodeGenRegisters.cpp1100 for (auto &Idx : SubRegIndices) in CodeGenRegBank()
1142 for (CodeGenSubRegIndex &SRI : SubRegIndices) { in CodeGenRegBank()
1203 SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1); in createSubRegIndex()
1204 return &SubRegIndices.back(); in createSubRegIndex()
1211 SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1); in getSubRegIdx()
1212 Idx = &SubRegIndices.back(); in getSubRegIdx()
1366 for (auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1387 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1406 for (auto &Idx2 : SubRegIndices) { in computeSubRegLaneMasks()
1462 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
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/external/llvm/lib/MC/
DMCRegisterInfo.cpp31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg()
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/
DMCRegisterInfo.cpp36 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg()
47 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex()
/external/capstone/
DMCRegisterInfo.c48 RI->SubRegIndices = SubIndices; in MCRegisterInfo_InitMCRegisterInfo()
111 uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; in MCRegisterInfo_getSubReg()
DMCRegisterInfo.h58 uint32_t SubRegIndices; member
88 uint16_t *SubRegIndices; // Pointer to the subreg lookup member
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h112 uint32_t SubRegIndices; member
168 const uint16_t *SubRegIndices; // Pointer to the subreg lookup variable
270 SubRegIndices = SubIndices; in InitMCRegisterInfo()
489 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; in MCSubRegIndexIterator()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCRegisterInfo.h112 uint32_t SubRegIndices; member
169 const uint16_t *SubRegIndices; // Pointer to the subreg lookup variable
270 SubRegIndices = SubIndices; in InitMCRegisterInfo()
512 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; in MCSubRegIndexIterator()
/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td66 let SubRegIndices = [subreg_l32, subreg_h32];
73 let SubRegIndices = [subreg_l64, subreg_h64];
180 let SubRegIndices = [subreg_r32];
187 let SubRegIndices = [subreg_l64, subreg_h64];
222 let SubRegIndices = [subreg_r64];
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZRegisterInfo.td81 let SubRegIndices = [subreg_32bit] in {
101 let SubRegIndices = [subreg_32bit, subreg_odd32] in {
112 let SubRegIndices = [subreg_even, subreg_odd],
142 let SubRegIndices = [subreg_32bit] in {
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td30 let SubRegIndices = [sub0, sub1];
40 let SubRegIndices = [sub0, sub1];
54 let SubRegIndices = [sub0, sub1];
64 let SubRegIndices = [sub0, sub1];
91 let SubRegIndices = [sub0, sub1];
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td39 let SubRegIndices = [sub_32];
56 let SubRegIndices = [sub_64];
71 let SubRegIndices = [sub_64];
79 let SubRegIndices = [sub_64];
88 let SubRegIndices = [sub_128];
193 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td67 let SubRegIndices = [subreg_l32, subreg_h32];
75 let SubRegIndices = [subreg_l64, subreg_h64];
191 let SubRegIndices = [subreg_r32];
198 let SubRegIndices = [subreg_l64, subreg_h64];
234 let SubRegIndices = [subreg_r64];
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td47 let SubRegIndices = [sub_32];
56 let SubRegIndices = [sub_lo, sub_hi];
62 let SubRegIndices = [sub_lo, sub_hi];
69 let SubRegIndices = [sub_64];
75 let SubRegIndices = [sub_lo, sub_hi];
191 let SubRegIndices = [sub_32] in {
247 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td38 let SubRegIndices = [sub_32];
45 let SubRegIndices = [sub_32];
62 let SubRegIndices = [sub_64];
77 let SubRegIndices = [sub_64];
85 let SubRegIndices = [sub_64];
201 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsRegisterInfo.td47 let SubRegIndices = [sub_32];
56 let SubRegIndices = [sub_lo, sub_hi];
62 let SubRegIndices = [sub_lo, sub_hi];
69 let SubRegIndices = [sub_64];
75 let SubRegIndices = [sub_lo, sub_hi];
191 let SubRegIndices = [sub_32] in {
247 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td57 let SubRegIndices = [sub0, sub1];
67 let SubRegIndices = [sub0, sub1];
85 let SubRegIndices = [sub0, sub1];
96 let SubRegIndices = [sub0, sub1];
106 let SubRegIndices = [sub0, sub1];
126 let SubRegIndices = [sub0, sub1];
268 let SubRegIndices = indices;
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsRegisterInfo.td40 let SubRegIndices = [sub_32];
52 let SubRegIndices = [sub_fpeven, sub_fpodd];
58 let SubRegIndices = [sub_32];
232 let SubRegIndices = [sub_32] in {
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td98 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
136 let SubRegIndices = [subreg_overflow];
166 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
182 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td113 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
119 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
128 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CostPerUse = 1,
141 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
154 let SubRegIndices = [sub_16bit, sub_16bit_hi], CostPerUse = 1,
167 let SubRegIndices = [sub_32bit] in {
252 let SubRegIndices = [sub_xmm] in {
260 let SubRegIndices = [sub_ymm] in {

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