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Searched refs:SubTarget (Results 1 – 13 of 13) sorted by relevance

/external/llvm/lib/Target/AVR/
DAVRTargetMachine.cpp49 SubTarget(TT, getCPU(CPU), FS, *this) { in AVRTargetMachine()
82 return &SubTarget; in getSubtargetImpl()
86 return &SubTarget; in getSubtargetImpl()
DAVRTargetMachine.h46 AVRSubtarget SubTarget; variable
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86IndirectBranchTracking.cpp90 const X86Subtarget &SubTarget = MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
101 TII = SubTarget.getInstrInfo(); in runOnMachineFunction()
102 EndbrOpcode = SubTarget.is64Bit() ? X86::ENDBR64 : X86::ENDBR32; in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRTargetMachine.cpp58 SubTarget(TT, getCPU(CPU), FS, *this) { in AVRTargetMachine()
95 return &SubTarget; in getSubtargetImpl()
99 return &SubTarget; in getSubtargetImpl()
DAVRTargetMachine.h52 AVRSubtarget SubTarget; variable
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.h34 PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td31 class SubTarget<bits<6> value> {
35 def HasAnySubT : SubTarget<0x3f>; // 111111
36 def HasV5SubT : SubTarget<0x3e>; // 111110
37 def HasV55SubT : SubTarget<0x3c>; // 111100
38 def HasV60SubT : SubTarget<0x38>; // 111000
157 SubTarget validSubTargets = HasAnySubT;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonBaseInfo.h31 enum SubTarget { enum
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonBaseInfo.h70 enum SubTarget { enum
DHexagonMCInstrInfo.cpp356 HexagonII::SubTarget Target = static_cast<HexagonII::SubTarget>( in getSubTarget()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMIRPrinter.cpp656 const auto &SubTarget = MF->getSubtarget(); in print() local
657 const auto *TRI = SubTarget.getRegisterInfo(); in print()
659 const auto *TII = SubTarget.getInstrInfo(); in print()
/external/llvm/lib/CodeGen/
DMIRPrinter.cpp543 const auto &SubTarget = MF->getSubtarget(); in print() local
544 const auto *TRI = SubTarget.getRegisterInfo(); in print()
546 const auto *TII = SubTarget.getInstrInfo(); in print()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInsertWaitcnts.cpp139 BlockWaitcntBrackets(const GCNSubtarget *SubTarget) : ST(SubTarget) { in BlockWaitcntBrackets() argument