1 //===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the AVR specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AVRTargetMachine.h"
15
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/TargetPassConfig.h"
18 #include "llvm/IR/Module.h"
19 #include "llvm/IR/LegacyPassManager.h"
20 #include "llvm/Support/TargetRegistry.h"
21
22 #include "AVRTargetObjectFile.h"
23 #include "AVR.h"
24 #include "MCTargetDesc/AVRMCTargetDesc.h"
25
26 namespace llvm {
27
28 /// Processes a CPU name.
getCPU(StringRef CPU)29 static StringRef getCPU(StringRef CPU) {
30 if (CPU.empty() || CPU == "generic") {
31 return "avr2";
32 }
33
34 return CPU;
35 }
36
getEffectiveRelocModel(Optional<Reloc::Model> RM)37 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
38 return RM.hasValue() ? *RM : Reloc::Static;
39 }
40
AVRTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,CodeModel::Model CM,CodeGenOpt::Level OL)41 AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
42 StringRef CPU, StringRef FS,
43 const TargetOptions &Options,
44 Optional<Reloc::Model> RM, CodeModel::Model CM,
45 CodeGenOpt::Level OL)
46 : LLVMTargetMachine(
47 T, "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-i64:8:8-f32:8:8-f64:8:8-n8", TT,
48 getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL),
49 SubTarget(TT, getCPU(CPU), FS, *this) {
50 this->TLOF = make_unique<AVRTargetObjectFile>();
51 initAsmInfo();
52 }
53
54 namespace {
55 /// AVR Code Generator Pass Configuration Options.
56 class AVRPassConfig : public TargetPassConfig {
57 public:
AVRPassConfig(AVRTargetMachine * TM,PassManagerBase & PM)58 AVRPassConfig(AVRTargetMachine *TM, PassManagerBase &PM)
59 : TargetPassConfig(TM, PM) {}
60
getAVRTargetMachine() const61 AVRTargetMachine &getAVRTargetMachine() const {
62 return getTM<AVRTargetMachine>();
63 }
64
65 bool addInstSelector() override;
66 void addPreSched2() override;
67 void addPreRegAlloc() override;
68 void addPreEmitPass() override;
69 };
70 } // namespace
71
createPassConfig(PassManagerBase & PM)72 TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
73 return new AVRPassConfig(this, PM);
74 }
75
LLVMInitializeAVRTarget()76 extern "C" void LLVMInitializeAVRTarget() {
77 // Register the target.
78 RegisterTargetMachine<AVRTargetMachine> X(TheAVRTarget);
79 }
80
getSubtargetImpl() const81 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
82 return &SubTarget;
83 }
84
getSubtargetImpl(const Function &) const85 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
86 return &SubTarget;
87 }
88
89 //===----------------------------------------------------------------------===//
90 // Pass Pipeline Configuration
91 //===----------------------------------------------------------------------===//
92
addInstSelector()93 bool AVRPassConfig::addInstSelector() {
94 return false;
95 }
96
addPreRegAlloc()97 void AVRPassConfig::addPreRegAlloc() {
98 }
99
addPreSched2()100 void AVRPassConfig::addPreSched2() { }
101
addPreEmitPass()102 void AVRPassConfig::addPreEmitPass() {
103 }
104
105 } // end of namespace llvm
106