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Searched refs:TBR (Results 1 – 15 of 15) sorted by relevance

/external/u-boot/board/renesas/sh7753evb/
Dspi-boot.c20 #define TBR 0xFE002000 macro
94 spi_write(M25_READ_4BYTE, TBR); in spi_read_flash()
95 spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */ in spi_read_flash()
98 spi_write(M25_READ, TBR); in spi_read_flash()
100 spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */ in spi_read_flash()
101 spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */ in spi_read_flash()
102 spi_write(addr & 0xFF, TBR); /* ADDR7-0 */ in spi_read_flash()
/external/u-boot/board/renesas/sh7757lcr/
Dspi-boot.c28 #define TBR 0xFE002000 macro
81 spi_write(M25_READ, TBR); in spi_read_flash()
82 spi_write((addr >> 16) & 0xFF, TBR); in spi_read_flash()
83 spi_write((addr >> 8) & 0xFF, TBR); in spi_read_flash()
84 spi_write(addr & 0xFF, TBR); in spi_read_flash()
/external/u-boot/board/renesas/sh7752evb/
Dspi-boot.c24 #define TBR 0xFE002000 macro
86 spi_write(M25_READ, TBR); in spi_read_flash()
87 spi_write((addr >> 16) & 0xFF, TBR); in spi_read_flash()
88 spi_write((addr >> 8) & 0xFF, TBR); in spi_read_flash()
89 spi_write(addr & 0xFF, TBR); in spi_read_flash()
/external/libyuv/files/tools/
DOWNERS2 # to owners-TBR new folders (assuming you have a regular review already,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td106 // Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
109 def TBR : SparcCtrlReg<0, "TBR">;
DSparcInstrInfo.td1021 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1033 let rs2 = 0, rs1 = 0, Uses=[TBR] in
1047 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1067 let Defs = [TBR], rd=0 in {
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td106 // Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
109 def TBR : SparcCtrlReg<0, "TBR">;
DSparcInstrInfo.td1014 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1026 let rs2 = 0, rs1 = 0, Uses=[TBR] in
1040 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1060 let Defs = [TBR], rd=0 in {
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrFormats.td145 class TBR<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
DMBlazeInstrInfo.td194 TBR<op, (outs GPR:$dst), (ins Od:$b, GPR:$c),
216 TBR<op, (outs GPR:$dst), (ins Od:$c, GPR:$b),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp854 case Sparc::TBR: in parseSparcAsmOperand()
1011 RegNo = Sparc::TBR; in matchRegisterName()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp868 case Sparc::TBR: in parseSparcAsmOperand()
1021 RegNo = Sparc::TBR; in matchRegisterName()
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart2.csv4264 ,"GB","TBR","Saint Brelade","Saint Brelade",,"1-------","RL","1101",,"4912N 00212W",""
8271 ,"ID","TBR","Telukbayur","Telukbayur","SB","1-3-----","RL","0501",,"0100S 10022E",
15216 ,"IT","TBR","Trebbo di Reno","Trebbo di Reno","BO","--3-----","RL","0901",,"4433N 01119E",
17168 ,"JP","TBR","Tabira","Tabira","42","1-------","AF","9907",,,
18925 ,"MK","TBR","Trubarevo","Trubarevo",,"--3-----","AC","9704",,,
D2013-1_UNLOCODE_CodeListPart1.csv3517 ,"AU","TBR","Tooborac","Tooborac","VIC","-----6--","RL","0901",,"3703S 14450E",
10756 ,"CA","TBR","Taber","Taber","AB","-2------","RL","0101",,"4947N 11209W",
14968 ,"CR","TBR","Tambor","Tambor","P","--3-----","RQ","0901",,"0943N 08502W",
16123 ,"CZ","TBR","Tabor","Tabor",,"-23-----","AA","9509",,,
24332 ,"DE","TBR","Trebur","Trebur","HE","--3-----","AF","9501",,,
30869 ,"ES","TBR","Tabara","Tabara","ZA","1-------","RQ","1001",,"4149N 00557W",
42852 ,"FR","TBR","Trets","Trets","14","-2------","RQ","0607",,,
D2013-1_UNLOCODE_CodeListPart3.csv3719 ,"PT","TBR","Terras de Bouro","Terras de Bouro","03","--3-----","RN","0401",,"4143N 00818W",
24804 ,"US","TBR","Statesboro","Statesboro","GA","---4----","AI","9601",,,