| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-const-a32.json | 35 "Teq", // TEQ{<c>}{<q>} <Rn>, #<const> ; A1
97 "Teq", // TEQ{<c>}{<q>} <Rn>, #<const> ; A1
|
| D | cond-rd-operand-const-t32.json | 38 "Teq", // TEQ{<c>}{<q>} <Rn>, #<const> ; T1
|
| D | cond-rd-operand-rn-shift-rs-a32.json | 35 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1
|
| D | cond-rd-operand-rn-shift-amount-1to31-a32.json | 35 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-operand-rn-shift-amount-1to32-a32.json | 35 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-operand-rn-a32.json | 43 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-operand-rn-shift-amount-1to31-t32.json | 40 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T1
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| D | cond-rd-operand-rn-shift-amount-1to32-t32.json | 41 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T1
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| D | cond-rd-operand-rn-t32.json | 51 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T1
|
| /external/tremolo/Tremolo/ |
| D | mdctLARM.s | 69 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
74 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
79 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
84 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
100 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
137 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
142 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
147 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
152 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
169 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
[all …]
|
| D | mdctARM.s | 71 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
76 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
81 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
86 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
102 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
139 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
144 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
149 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
154 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
171 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
[all …]
|
| /external/v8/src/mips/ |
| D | constants-mips.h | 541 TEQ = ((6U << 3) + 4), enumerator
1296 FunctionFieldToBitNumber(TEQ) | FunctionFieldToBitNumber(TNE) |
1848 case TEQ: in IsTrap()
|
| D | disasm-mips.cc | 482 case TEQ: in PrintCode()
1446 case TEQ: in DecodeTypeRegisterSPECIAL()
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 537 TEQ = ((6U << 3) + 4), enumerator
1342 FunctionFieldToBitNumber(TEQ) | FunctionFieldToBitNumber(TNE) |
1931 case TEQ: in IsTrap()
|
| D | disasm-mips64.cc | 523 case TEQ: in PrintCode()
1681 case TEQ: in DecodeTypeRegisterSPECIAL()
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 130 TEQ = 9 << 21, // Test Equivalence. enumerator
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| D | disasm-arm.cc | 996 case TEQ: { in DecodeType01()
|
| D | assembler-arm.cc | 1184 (opcode == TEQ) || (opcode == TST) || (opcode == MOV) || in AddrMode1()
1188 (opcode == TEQ) || (opcode == TST)); in AddrMode1()
1552 AddrMode1(cond | TEQ | S, no_reg, src1, src2); in teq()
|
| /external/llvm/test/MC/ARM/ |
| D | diagnostics.s | 668 TEQ r7, #-2149, #0
669 TEQ r7, #100, #1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | diagnostics.s | 749 TEQ r7, #-2149, #0
750 TEQ r7, #100, #1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 71 TAILCALLREGHB, TEQ, TEQI, TGE, TGEI, TGEIU,
|
| D | MipsFastISel.cpp | 1916 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3051 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3068 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3084 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3119 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); in expandDiv()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3995 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4027 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4047 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4093 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); in expandDivRem()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1690 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
|