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Searched refs:TRC (Results 1 – 25 of 40) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXMachineFunctionInfo.h103 void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) { in addVirtualRegister() argument
108 UsedRegs[TRC].push_back(Reg); in addVirtualRegister()
109 if (TRC == PTX::RegPredRegisterClass) in addVirtualRegister()
111 else if (TRC == PTX::RegI16RegisterClass) in addVirtualRegister()
113 else if (TRC == PTX::RegI32RegisterClass) in addVirtualRegister()
115 else if (TRC == PTX::RegI64RegisterClass) in addVirtualRegister()
117 else if (TRC == PTX::RegF32RegisterClass) in addVirtualRegister()
119 else if (TRC == PTX::RegF64RegisterClass) in addVirtualRegister()
124 name += utostr(UsedRegs[TRC].size() - 1); in addVirtualRegister()
142 unsigned getNumRegistersForClass(const TargetRegisterClass *TRC) const { in getNumRegistersForClass() argument
[all …]
DPTXISelLowering.cpp239 TargetRegisterClass* TRC = getRegClassFor(RegVT); in LowerFormalArguments() local
244 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC); in LowerFormalArguments()
300 TargetRegisterClass* TRC = 0; in LowerReturn() local
304 TRC = PTX::RegPredRegisterClass; in LowerReturn()
307 TRC = PTX::RegI16RegisterClass; in LowerReturn()
310 TRC = PTX::RegI32RegisterClass; in LowerReturn()
313 TRC = PTX::RegI64RegisterClass; in LowerReturn()
316 TRC = PTX::RegF32RegisterClass; in LowerReturn()
319 TRC = PTX::RegF64RegisterClass; in LowerReturn()
325 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC); in LowerReturn()
DPTXMFInfoExtract.cpp58 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in runOnMachineFunction() local
59 MFI->addVirtualRegister(TRC, Reg); in runOnMachineFunction()
DPTXAsmPrinter.cpp57 const TargetRegisterClass *TRC = MRI.getRegClass(RegNo); in getRegisterTypeName() local
60 if (PTX::cls ## RegisterClass == TRC) return # clsstr; in getRegisterTypeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp75 unsigned Lane, const TargetRegisterClass *TRC);
98 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
134 const TargetRegisterClass *TRC) { in usesRegClass() argument
140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
142 return TRC->contains(Reg); in usesRegClass()
272 const TargetRegisterClass *TRC = in optimizeSDPattern() local
274 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
437 const TargetRegisterClass *TRC) { in createExtractSubreg() argument
438 unsigned Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
DARMISelLowering.cpp8252 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass in SetupEntryBlockForSjLj() local
8271 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
8277 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
8283 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
8301 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
8306 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
8311 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
8316 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
8322 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
8337 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
[all …]
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp77 unsigned Lane, const TargetRegisterClass *TRC);
100 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
136 const TargetRegisterClass *TRC) { in usesRegClass() argument
142 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
144 return TRC->contains(Reg); in usesRegClass()
278 const TargetRegisterClass *TRC = in optimizeSDPattern() local
280 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
447 const TargetRegisterClass *TRC) { in createExtractSubreg() argument
448 unsigned Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
DARMISelLowering.cpp7303 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass in SetupEntryBlockForSjLj() local
7322 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
7327 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
7332 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
7349 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
7353 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
7358 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
7362 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
7367 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
7381 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
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/external/u-boot/board/technologic/ts4600/
Diomux.c119 #define TRC 0xd macro
121 #define HW_DRAM_CTL41_CONFIG (TPDEX << 24 | TRCD_INT << 8 | TRC)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyAsmPrinter.cpp51 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
54 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp494 const TargetRegisterClass *TRC = in EmitSubregNode() local
503 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
509 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
523 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
628 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
630 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyAsmPrinter.cpp97 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
99 if (TRC->hasType(T)) in getRegType()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp517 const TargetRegisterClass *TRC = in EmitSubregNode() local
535 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
541 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
556 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
666 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
668 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp452 const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0)); in EmitSubregNode() local
465 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
478 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
579 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
581 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp2132 TargetRegisterClass *TRC = 0; in Select() local
2134 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; in Select()
2135 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; in Select()
2138 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); in Select()
2161 TargetRegisterClass *TRC = 0; in Select() local
2163 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break; in Select()
2164 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; in Select()
2165 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; in Select()
2168 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); in Select()
/external/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp430 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
431 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
DRegAllocPBQP.cpp576 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
585 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp5197 TargetRegisterClass *TRC = in EmitAtomicBinary() local
5199 unsigned scratch = MRI.createVirtualRegister(TRC); in EmitAtomicBinary()
5200 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); in EmitAtomicBinary()
5307 TargetRegisterClass *TRC = in EmitAtomicBinaryMinMax() local
5309 unsigned scratch = MRI.createVirtualRegister(TRC); in EmitAtomicBinaryMinMax()
5310 unsigned scratch2 = MRI.createVirtualRegister(TRC); in EmitAtomicBinaryMinMax()
5417 TargetRegisterClass *TRC = in EmitAtomicBinary64() local
5419 unsigned storesuccess = MRI.createVirtualRegister(TRC); in EmitAtomicBinary64()
5571 const TargetRegisterClass *TRC = in SetupEntryBlockForSjLj() local
5592 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
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DARMLoadStoreOptimizer.cpp1679 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI); in RescheduleOps() local
1680 MRI->constrainRegClass(EvenReg, TRC); in RescheduleOps()
1681 MRI->constrainRegClass(OddReg, TRC); in RescheduleOps()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2531 const TargetRegisterClass *TRC; in Select() local
2533 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; in Select()
2534 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; in Select()
2537 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); in Select()
2566 const TargetRegisterClass *TRC; in Select() local
2568 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break; in Select()
2569 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; in Select()
2570 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; in Select()
2573 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); in Select()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp497 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
498 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
DRegAllocPBQP.cpp605 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
613 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86AvoidStoreForwardingBlocks.cpp561 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
563 return TRI->getRegSizeInBits(*TRC) / 8; in getRegSizeInBytes()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp719 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
722 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp1685 const TargetRegisterClass *TRC; in createVR() local
1687 TRC = &Hexagon::PredRegsRegClass; in createVR()
1689 TRC = &Hexagon::IntRegsRegClass; in createVR()
1691 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
1696 unsigned NewReg = MRI.createVirtualRegister(TRC); in createVR()

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